/*==============================================================================
 Copyright (c) 2015-2018 Qualcomm Technologies, Inc.
 All Rights Reserved.
 Confidential and Proprietary - Qualcomm Technologies, Inc.
==============================================================================*/
#ifndef TITAN170_IFE_LITE_H
#define TITAN170_IFE_LITE_H

/*----------------------------------------------------------------------
        Offset and Mask
----------------------------------------------------------------------*/

#define IFE_LITE_REGS_FIRST 0x0 

#define IFE_LITE_REGS_LAST 0x49d4 

#define IFE_LITE_REGS_COUNT 0x1bd 

#define regIFE_LITE_IFE_LITE_VFE_HW_VERSION 0x0  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_HW_VERSION_INCR_VERSION_MASK 0xffff
#define IFE_LITE_IFE_LITE_VFE_HW_VERSION_INCR_VERSION_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_HW_VERSION_MINOR_VERSION_MASK 0xfff0000
#define IFE_LITE_IFE_LITE_VFE_HW_VERSION_MINOR_VERSION_SHIFT 0x10
#define IFE_LITE_IFE_LITE_VFE_HW_VERSION_MAJOR_VERSION_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_VFE_HW_VERSION_MAJOR_VERSION_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_VFE_HW_CAPABILITY 0x4  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_BUS_FEATURE_MASK 0x7
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_BUS_FEATURE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_THREE_D_FEATURE_MASK 0x8
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_THREE_D_FEATURE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_UNUSED0_MASK 0xfff0
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_MAIN_LINE_BUFFER_FEATURE_MASK 0x1fff0000
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_MAIN_LINE_BUFFER_FEATURE_SHIFT 0x10
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_RDI_FEATURE_MASK 0x60000000
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_RDI_FEATURE_SHIFT 0x1d
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_INPUT_FORMAT_FEATURE_MASK 0x80000000
#define IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY_INPUT_FORMAT_FEATURE_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE 0x8  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_PEDESTAL_FEATURE_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_PEDESTAL_FEATURE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_BLACK_FEATURE_MASK 0x2
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_BLACK_FEATURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_DEMUX_FEATURE_MASK 0x4
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_DEMUX_FEATURE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_CHROMA_UPSAMPLE_FEATURE_MASK 0x8
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_CHROMA_UPSAMPLE_FEATURE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_HDR_RECON_FEATURE_MASK 0x10
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_HDR_RECON_FEATURE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_HDR_MAC_FEATURE_MASK 0x20
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_HDR_MAC_FEATURE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_BPC_FEATURE_MASK 0x40
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_BPC_FEATURE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_ABF_FEATURE_MASK 0x80
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_ABF_FEATURE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_ROLLOFF_FEATURE_MASK 0x100
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_ROLLOFF_FEATURE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_GIC_FEATURE_MASK 0x200
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_GIC_FEATURE_SHIFT 0x9
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_DEMO_FEATURE_MASK 0xc00
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_DEMO_FEATURE_SHIFT 0xa
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_BLACK_LEVEL_FEATURE_MASK 0x1000
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_BLACK_LEVEL_FEATURE_SHIFT 0xc
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_PDAF_FEATURE_MASK 0x2000
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_PDAF_FEATURE_SHIFT 0xd
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_UNUSED0_MASK 0xffffc000
#define IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE_UNUSED0_SHIFT 0xe

#define regIFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE 0xc  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_HDR_BE_FEATURE_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_HDR_BE_FEATURE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_HDR_BHIST_FEATURE_MASK 0x2
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_HDR_BHIST_FEATURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_BAF_FEATURE_MASK 0x4
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_BAF_FEATURE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_AWB_BG_FEATURE_MASK 0x8
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_AWB_BG_FEATURE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_SKIN_BHIST_FEATURE_MASK 0x10
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_SKIN_BHIST_FEATURE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_RS_FEATURE_MASK 0x20
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_RS_FEATURE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_CS_FEATURE_MASK 0x40
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_CS_FEATURE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_IHIST_FEATURE_MASK 0x80
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_IHIST_FEATURE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_AEC_BG_FEATURE_MASK 0x100
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_AEC_BG_FEATURE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_UNUSED0_MASK 0xfffffe00
#define IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE_UNUSED0_SHIFT 0x9

#define regIFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE 0x10  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_CAC_SNR_FEATURE_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_CAC_SNR_FEATURE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_COLOR_CORRECT_FEATURE_MASK 0x2
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_COLOR_CORRECT_FEATURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_GTM_FEATURE_MASK 0x4
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_GTM_FEATURE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_RGB_LUT_FEATURE_MASK 0x8
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_RGB_LUT_FEATURE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_LTM_FEATURE_MASK 0x10
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_LTM_FEATURE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_CHROMA_ENHAN_FEATURE_MASK 0x20
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_CHROMA_ENHAN_FEATURE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_CHROMA_SUPPRESS_MCE_FEATURE_MASK 0x40
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_CHROMA_SUPPRESS_MCE_FEATURE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_SKIN_ENHAN_FEATURE_MASK 0x80
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_SKIN_ENHAN_FEATURE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE 0x14  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_CST_FEATURE_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_CST_FEATURE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_UNUSED0_MASK 0x6
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_UNUSED0_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_SCALE_FEATURE_MASK 0x38
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_SCALE_FEATURE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_CROP_FEATURE_MASK 0x1c0
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_CROP_FEATURE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_REALIGN_BUF_FEATURE_MASK 0x200
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_REALIGN_BUF_FEATURE_SHIFT 0x9
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_Y_1ST_FEATURE_MASK 0x400
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_Y_1ST_FEATURE_SHIFT 0xa
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_Y_2ND_FEATURE_MASK 0x800
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_Y_2ND_FEATURE_SHIFT 0xb
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_C_1ST_FEATURE_MASK 0x1000
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_C_1ST_FEATURE_SHIFT 0xc
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_C_2ND_FEATURE_MASK 0x2000
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_DS_4TO1_C_2ND_FEATURE_SHIFT 0xd
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_R2PD_1ST_FEATURE_MASK 0x4000
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_R2PD_1ST_FEATURE_SHIFT 0xe
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_R2PD_2ND_FEATURE_MASK 0x8000
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_R2PD_2ND_FEATURE_SHIFT 0xf
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_UNUSED1_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE_UNUSED1_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD 0x18  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_CORE_RESET_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_CORE_RESET_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_UNUSED0_MASK 0x2
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_UNUSED0_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_BUS_HW_RESET_MASK 0x4
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_BUS_HW_RESET_SHIFT 0x2
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_BUS_SW_RESET_MASK 0x8
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_BUS_SW_RESET_SHIFT 0x3
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_REGISTER_RESET_MASK 0x10
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_REGISTER_RESET_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_UNUSED1_MASK 0x1e0
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_UNUSED1_SHIFT 0x5
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_IDLE_CGC_RESET_MASK 0x200
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_IDLE_CGC_RESET_SHIFT 0x9
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_0_RESET_MASK 0x400
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_0_RESET_SHIFT 0xa
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_1_RESET_MASK 0x800
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_1_RESET_SHIFT 0xb
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_2_RESET_MASK 0x1000
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_2_RESET_SHIFT 0xc
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_3_RESET_MASK 0x2000
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RDI_3_RESET_SHIFT 0xd
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_UNUSED2_MASK 0x3fffc000
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_UNUSED2_SHIFT 0xe
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_VFE_DOMAIN_RESET_MASK 0x40000000
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_VFE_DOMAIN_RESET_SHIFT 0x1e
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RESET_BYPASS_MASK 0x80000000
#define IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD_RESET_BYPASS_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE 0x3c  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE_BUS_WR_IF_CGC_OVERRIDE_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE_BUS_WR_IF_CGC_OVERRIDE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE_TESTGEN_CGC_OVERRIDE_MASK 0x2
#define IFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE_TESTGEN_CGC_OVERRIDE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_VFE_CORE_CFG 0x40  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_CORE_CFG_UNUSED0_MASK 0x7f
#define IFE_LITE_IFE_LITE_VFE_CORE_CFG_UNUSED0_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_CORE_CFG_CAMNOC_HALT_DIS_MASK 0x80
#define IFE_LITE_IFE_LITE_VFE_CORE_CFG_CAMNOC_HALT_DIS_SHIFT 0x7
#define IFE_LITE_IFE_LITE_VFE_CORE_CFG_UNUSED1_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_VFE_CORE_CFG_UNUSED1_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_VFE_IRQ_CMD 0x58  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_IRQ_CMD_GLOBAL_CLEAR_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_IRQ_CMD_GLOBAL_CLEAR_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_IRQ_CMD_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_VFE_IRQ_CMD_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_VFE_IRQ_MASK_0 0x5c  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_IRQ_MASK_0_MASK_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_VFE_IRQ_MASK_0_MASK_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_VFE_IRQ_MASK_1 0x60  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_IRQ_MASK_1_MASK_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_VFE_IRQ_MASK_1_MASK_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_0 0x64  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_0_CLEAR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_0_CLEAR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_1 0x68  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_1_CLEAR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_1_CLEAR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_VFE_IRQ_STATUS_0 0x6c  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_IRQ_STATUS_0_STATUS_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_VFE_IRQ_STATUS_0_STATUS_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_VFE_IRQ_STATUS_1 0x70  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_IRQ_STATUS_1_STATUS_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_VFE_IRQ_STATUS_1_STATUS_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_VFE_VIOLATION_STATUS 0x7c  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_VIOLATION_STATUS_STATUS_MASK 0x3f
#define IFE_LITE_IFE_LITE_VFE_VIOLATION_STATUS_STATUS_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_VIOLATION_STATUS_UNUSED0_MASK 0xffffffc0
#define IFE_LITE_IFE_LITE_VFE_VIOLATION_STATUS_UNUSED0_SHIFT 0x6

#define regIFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD 0x4ac  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_UPDATE_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_UPDATE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI0_UPDATE_MASK 0x2
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI0_UPDATE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI1_UPDATE_MASK 0x4
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI1_UPDATE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI2_UPDATE_MASK 0x8
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI2_UPDATE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI3_UPDATE_MASK 0x10
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_RDI3_UPDATE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_VFE_DIAG_CFG 0xc48  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_DIAG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_DIAG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_SENSOR_SEL_MASK 0xe
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_SENSOR_SEL_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI3_FRM_CNT_EN_MASK 0x10
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI3_FRM_CNT_EN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI0_FRM_CNT_EN_MASK 0x20
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI0_FRM_CNT_EN_SHIFT 0x5
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI1_FRM_CNT_EN_MASK 0x40
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI1_FRM_CNT_EN_SHIFT 0x6
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI2_FRM_CNT_EN_MASK 0x80
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI2_FRM_CNT_EN_SHIFT 0x7
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_VFE_DIAG_CFG_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS 0xc4c  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_SENSOR_HBI_MASK 0x3fff
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_SENSOR_HBI_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_SENSOR_NEQ_HBI_MASK 0x4000
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_SENSOR_NEQ_HBI_SHIFT 0xe
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_SENSOR_HBI_MIN_ERROR_MASK 0x8000
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_SENSOR_HBI_MIN_ERROR_SHIFT 0xf
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_VFE_STM_CFG 0xc50  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_STM_CFG_OUTPUT_SEL_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_STM_CFG_OUTPUT_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_STM_CFG_EVENT_SITE_SEL_MASK 0x2
#define IFE_LITE_IFE_LITE_VFE_STM_CFG_EVENT_SITE_SEL_SHIFT 0x1
#define IFE_LITE_IFE_LITE_VFE_STM_CFG_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_VFE_STM_CFG_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_VFE_TESTBUS_SEL 0xc80  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_BUS_SEL_MASK 0xf
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_BUS_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_MASK 0x70
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_SHIFT 0x4
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_TESTBUS_EN_MASK 0x80
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_TESTBUS_EN_SHIFT 0x7
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_VFE_PWR_ISO_CFG 0xce0  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_PWR_ISO_CFG_PWR_ISO_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_VFE_PWR_ISO_CFG_PWR_ISO_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_PWR_ISO_CFG_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_VFE_PWR_ISO_CFG_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS 0xd58  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI3_FRM_CNT_MASK 0xff
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI3_FRM_CNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI0_FRM_CNT_MASK 0xff00
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI0_FRM_CNT_SHIFT 0x8
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI1_FRM_CNT_MASK 0xff0000
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI1_FRM_CNT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI2_FRM_CNT_MASK 0xff000000
#define IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS_RDI2_FRM_CNT_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_VFE_VFE_SPARE 0xf90  /*register offset*/
#define IFE_LITE_IFE_LITE_VFE_VFE_SPARE_SPARE_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_VFE_VFE_SPARE_SPARE_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_HW_VERSION 0x2000  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_HW_VERSION_STEP_MASK 0xffff
#define IFE_LITE_IFE_LITE_BUS_WR_HW_VERSION_STEP_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_HW_VERSION_REV_MASK 0xfff0000
#define IFE_LITE_IFE_LITE_BUS_WR_HW_VERSION_REV_SHIFT 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_HW_VERSION_GEN_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_BUS_WR_HW_VERSION_GEN_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY 0x2004  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_FEATURE_MASK 0xff
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_FEATURE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_LITE_MASK 0xff00
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_LITE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_UBWC_MASK 0xff0000
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_UBWC_SHIFT 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_REG_MASK 0xff000000
#define IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY_REG_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_SW_RESET 0x2008  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_SW_RESET_SW_RESET_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_SW_RESET_SW_RESET_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_SW_RESET_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_SW_RESET_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_CGC_OVERRIDE 0x200c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIGE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_CGC_OVERRIDE_CGC_OVERRIGE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_CGC_OVERRIDE_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_CGC_OVERRIDE_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_0 0x2010  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_0_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_1 0x2014  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_1_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_1_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_1_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_1_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_2 0x2018  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_2_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_2_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_2_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_2_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_3 0x201c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_3_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_3_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_3_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_3_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_4 0x2020  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_4_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_4_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_4_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_4_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_5 0x2024  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_5_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_5_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_5_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_5_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_CFG 0x2028  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_CFG_INTRA_CLIENT_EN_MASK 0xfff
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_CFG_INTRA_CLIENT_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_CFG_UNUSED0_MASK 0xfffff000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_CFG_UNUSED0_SHIFT 0xc

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_0 0x202c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_0_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_0_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_0_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_0_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_1 0x2030  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_1_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_1_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_1_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_1_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_2 0x2034  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_2_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_2_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_2_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_2_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_3 0x2038  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_3_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_3_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_3_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_3_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_4 0x203c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_4_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_4_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_4_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_4_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_5 0x2040  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_5_MASK_VEC_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_5_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_5_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_5_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0 0x2044  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_RESET_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_RESET_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP0_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP0_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP1_BUF_DONE_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP1_BUF_DONE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP2_BUF_DONE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP2_BUF_DONE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP3_BUF_DONE_MASK 0x100
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP3_BUF_DONE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP4_BUF_DONE_MASK 0x200
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP4_BUF_DONE_SHIFT 0x9
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP5_BUF_DONE_MASK 0x400
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP5_BUF_DONE_SHIFT 0xa
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_ERROR_MASK 0x800
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_ERROR_SHIFT 0xb
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_OVERWRITE_MASK 0x1000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_COMP_OVERWRITE_SHIFT 0xc
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_OVERFLOW_ERROR_MASK 0x2000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_OVERFLOW_ERROR_SHIFT 0xd
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_VIOLATION_MASK 0x4000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_VIOLATION_SHIFT 0xe
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1 0x2048  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_WR_CLIENT_BUF_DONE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED0_MASK 0xfffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_EARLY_DONE_MASK 0x3000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_EARLY_DONE_SHIFT 0x18
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED1_MASK 0xfc000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1_UNUSED1_SHIFT 0x1a

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2 0x204c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP0_BUF_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP0_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP1_BUF_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP1_BUF_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP2_BUF_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP2_BUF_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP3_BUF_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP3_BUF_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP4_BUF_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP4_BUF_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP5_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP5_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP_ERROR_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP_ERROR_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP_OVERWRITE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_DUAL_COMP_OVERWRITE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0 0x2050  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_RESET_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_RESET_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP0_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP0_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP1_BUF_DONE_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP1_BUF_DONE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP2_BUF_DONE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP2_BUF_DONE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP3_BUF_DONE_MASK 0x100
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP3_BUF_DONE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP4_BUF_DONE_MASK 0x200
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP4_BUF_DONE_SHIFT 0x9
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP5_BUF_DONE_MASK 0x400
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP5_BUF_DONE_SHIFT 0xa
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_ERROR_MASK 0x800
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_ERROR_SHIFT 0xb
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_OVERWRITE_MASK 0x1000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_COMP_OVERWRITE_SHIFT 0xc
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_OVERFLOW_ERROR_MASK 0x2000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_OVERFLOW_ERROR_SHIFT 0xd
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_VIOLATION_MASK 0x4000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_VIOLATION_SHIFT 0xe
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1 0x2054  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_WR_CLIENT_BUF_DONE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED0_MASK 0xfffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_EARLY_DONE_MASK 0x3000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_EARLY_DONE_SHIFT 0x18
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED1_MASK 0xfc000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1_UNUSED1_SHIFT 0x1a

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2 0x2058  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP0_BUF_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP0_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP1_BUF_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP1_BUF_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP2_BUF_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP2_BUF_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP3_BUF_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP3_BUF_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP4_BUF_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP4_BUF_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP5_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP5_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP_ERROR_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP_ERROR_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP_OVERWRITE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_DUAL_COMP_OVERWRITE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0 0x205c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_RESET_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_RESET_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP0_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP0_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP1_BUF_DONE_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP1_BUF_DONE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP2_BUF_DONE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP2_BUF_DONE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP3_BUF_DONE_MASK 0x100
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP3_BUF_DONE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP4_BUF_DONE_MASK 0x200
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP4_BUF_DONE_SHIFT 0x9
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP5_BUF_DONE_MASK 0x400
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP5_BUF_DONE_SHIFT 0xa
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_ERROR_MASK 0x800
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_ERROR_SHIFT 0xb
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_OVERWRITE_MASK 0x1000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_COMP_OVERWRITE_SHIFT 0xc
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_OVERFLOW_ERROR_MASK 0x2000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_OVERFLOW_ERROR_SHIFT 0xd
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_VIOLATION_MASK 0x4000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_VIOLATION_SHIFT 0xe
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1 0x2060  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_WR_CLIENT_BUF_DONE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED0_MASK 0xfffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_EARLY_DONE_MASK 0x3000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_EARLY_DONE_SHIFT 0x18
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED1_MASK 0xfc000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1_UNUSED1_SHIFT 0x1a

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2 0x2064  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP0_BUF_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP0_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP1_BUF_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP1_BUF_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP2_BUF_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP2_BUF_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP3_BUF_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP3_BUF_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP4_BUF_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP4_BUF_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP5_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP5_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP_ERROR_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP_ERROR_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP_OVERWRITE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_DUAL_COMP_OVERWRITE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD 0x2068  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_CLEAR_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_CLEAR_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED0_MASK 0xe
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED0_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_SET_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_SET_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_ERROR_STATUS 0x206c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_ERROR_STATUS_CLIENT_COMP_IRQ_ERROR_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_ERROR_STATUS_CLIENT_COMP_IRQ_ERROR_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_ERROR_STATUS_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_ERROR_STATUS_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_OVERWRITE_ERROR_STATUS 0x2070  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_OVERWRITE_ERROR_STATUS_CLIENT_COMP_OVERWRITE_ERROR_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_OVERWRITE_ERROR_STATUS_CLIENT_COMP_OVERWRITE_ERROR_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_OVERWRITE_ERROR_STATUS_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_OVERWRITE_ERROR_STATUS_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS 0x2074  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_SLV0_COMP_IRQ_ERROR_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_SLV0_COMP_IRQ_ERROR_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_SLV1_COMP_IRQ_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_SLV1_COMP_IRQ_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_CLIENT_COMP_IRQ_ERROR_MASK 0x3c
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_CLIENT_COMP_IRQ_ERROR_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_UNUSED0_MASK 0xffffffc0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS_UNUSED0_SHIFT 0x6

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS 0x2078  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_SLV0_COMP_OVERWRITE_ERROR_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_SLV0_COMP_OVERWRITE_ERROR_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_SLV1_COMP_OVERWRITE_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_SLV1_COMP_OVERWRITE_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_CLIENT_COMP_OVERWRITE_ERROR_MASK 0x3c
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_CLIENT_COMP_OVERWRITE_ERROR_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_UNUSED0_MASK 0xffffffc0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS_UNUSED0_SHIFT 0x6

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG 0x207c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG_MODE_MASK 0xff
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG_INTRA_CLIENT_EN_MASK 0xffff00
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG_INTRA_CLIENT_EN_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_FRAME_HEADER 0x2080  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_FRAME_HEADER_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_FRAME_HEADER_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_FRAME_HEADER_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_FRAME_HEADER_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_NO_SYNC 0x2084  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_NO_SYNC_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_NO_SYNC_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_NO_SYNC_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_NO_SYNC_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_0 0x2088  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_0_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_0_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_0_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_0_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_1 0x208c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_1_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_1_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_1_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_1_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_2 0x2090  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_2_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_2_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_2_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_2_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_3 0x2094  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_3_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_3_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_3_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_3_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_4 0x2098  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_4_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_4_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_4_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_4_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_5 0x209c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_5_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_5_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_5_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_5_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_6 0x20a0  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_6_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_6_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_6_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_6_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_7 0x20a4  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_7_EN_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_7_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_7_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_7_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS 0x20a8  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_FIFO_STATUS_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_FIFO_STATUS_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0 0x20ac  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0_CFG0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0_CFG0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1 0x20b0  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1_CFG1_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1_CFG1_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG2 0x20b4  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG2_CFG2_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG2_CFG2_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG3 0x20b8  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG3_CFG3_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG3_CFG3_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0 0x20bc  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_RESET_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_RESET_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE0_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE0_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE1_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE1_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE2_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE2_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE3_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_REG_UPDATE3_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP0_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP0_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP1_BUF_DONE_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP1_BUF_DONE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP2_BUF_DONE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP2_BUF_DONE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP3_BUF_DONE_MASK 0x100
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP3_BUF_DONE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP4_BUF_DONE_MASK 0x200
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP4_BUF_DONE_SHIFT 0x9
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP5_BUF_DONE_MASK 0x400
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP5_BUF_DONE_SHIFT 0xa
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_ERROR_MASK 0x800
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_ERROR_SHIFT 0xb
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_OVERWRITE_MASK 0x1000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_COMP_OVERWRITE_SHIFT 0xc
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_OVERFLOW_ERROR_MASK 0x2000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_OVERFLOW_ERROR_SHIFT 0xd
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_VIOLATION_MASK 0x4000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_VIOLATION_SHIFT 0xe
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1 0x20c0  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_WR_CLIENT_BUF_DONE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_WR_CLIENT_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED0_MASK 0xfffff0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_EARLY_DONE_MASK 0x3000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_EARLY_DONE_SHIFT 0x18
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED1_MASK 0xfc000000
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1_UNUSED1_SHIFT 0x1a

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2 0x20c4  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP0_BUF_DONE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP0_BUF_DONE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP1_BUF_DONE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP1_BUF_DONE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP2_BUF_DONE_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP2_BUF_DONE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP3_BUF_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP3_BUF_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP4_BUF_DONE_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP4_BUF_DONE_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP5_BUF_DONE_MASK 0x20
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP5_BUF_DONE_SHIFT 0x5
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP_ERROR_MASK 0x40
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP_ERROR_SHIFT 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP_OVERWRITE_MASK 0x80
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_DUAL_COMP_OVERWRITE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_MISR_RESET 0x20c8  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_MISR_RESET_RESET_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_MISR_RESET_RESET_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_MISR_RESET_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_MISR_RESET_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_BUS_WR_PWR_ISO_CFG 0x20cc  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_PWR_ISO_CFG_PWR_ISO_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_PWR_ISO_CFG_PWR_ISO_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_PWR_ISO_CFG_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_BUS_WR_PWR_ISO_CFG_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG4 0x20d0  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG4_CFG4_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG4_CFG4_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL 0x211c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_TEST_BUS_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_TEST_BUS_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_MASK 0x1f0
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_TEST_BUS_CLIENT_SEL_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_MASK 0xfe00
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_TEST_BUS_INTERNAL_SEL_SHIFT 0x9
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_UNUSED1_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL_UNUSED1_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_SPARE 0x2120  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_SPARE_SPARE_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_SPARE_SPARE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_SPARE_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_BUS_WR_SPARE_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_0 0x2200  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_1 0x2204  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG 0x2208  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_VIRTUALFRAME_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_VIRTUALFRAME_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER 0x220c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAME_HEADER_CFG 0x2210  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE 0x2214  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET 0x2218  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG 0x221c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG 0x2220  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG 0x2224  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_WR_STRIDE 0x2228  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD 0x2248  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN 0x224c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PERIOD 0x2250  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PATTERN 0x2254  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_INCR 0x2258  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_INCR_ADDR_FRAME_INCR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_INCR_ADDR_FRAME_INCR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BURST_LIMIT_CFG 0x225c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG 0x2260  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL 0x2264  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_VAL 0x2268  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_VAL_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_VAL_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG 0x226c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_0 0x2270  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_1 0x2274  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_0 0x2300  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_1 0x2304  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG 0x2308  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_VIRTUALFRAME_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_VIRTUALFRAME_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER 0x230c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAME_HEADER_CFG 0x2310  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE 0x2314  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET 0x2318  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG 0x231c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG 0x2320  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG 0x2324  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_WR_STRIDE 0x2328  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD 0x2348  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN 0x234c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PERIOD 0x2350  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PATTERN 0x2354  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_INCR 0x2358  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_INCR_ADDR_FRAME_INCR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_INCR_ADDR_FRAME_INCR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BURST_LIMIT_CFG 0x235c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG 0x2360  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL 0x2364  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_VAL 0x2368  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_VAL_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_VAL_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG 0x236c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_0 0x2370  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_1 0x2374  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_0 0x2400  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_1 0x2404  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG 0x2408  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_VIRTUALFRAME_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_VIRTUALFRAME_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER 0x240c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAME_HEADER_CFG 0x2410  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE 0x2414  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET 0x2418  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG 0x241c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG 0x2420  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG 0x2424  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_WR_STRIDE 0x2428  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD 0x2448  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN 0x244c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PERIOD 0x2450  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PATTERN 0x2454  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_INCR 0x2458  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_INCR_ADDR_FRAME_INCR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_INCR_ADDR_FRAME_INCR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BURST_LIMIT_CFG 0x245c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG 0x2460  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL 0x2464  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_VAL 0x2468  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_VAL_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_VAL_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG 0x246c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_0 0x2470  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_1 0x2474  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_0 0x2500  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_0_LAST_CONSUMED_CLIENT_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_1 0x2504  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_1_LAST_CONSUMED_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG 0x2508  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_VIRTUALFRAME_MASK 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_VIRTUALFRAME_SHIFT 0x2
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER 0x250c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAME_HEADER_CFG 0x2510  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAME_HEADER_CFG_LOCAL_ID_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAME_HEADER_CFG_LOCAL_ID_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE 0x2514  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE_ADDR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE_ADDR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET 0x2518  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET_OFFSET_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET_OFFSET_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG 0x251c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG_WIDTH_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG_WIDTH_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG 0x2520  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_HEIGHT_MASK 0xffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG 0x2524  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_ALIGNMENT_MASK 0x10
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG_PACKER_CFG_ALIGNMENT_SHIFT 0x4
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_WR_STRIDE 0x2528  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_WR_STRIDE_WR_STRIDE_MASK 0x1fffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_WR_STRIDE_WR_STRIDE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_WR_STRIDE_UNUSED0_MASK 0xffe00000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_WR_STRIDE_UNUSED0_SHIFT 0x15

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD 0x2548  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN 0x254c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PERIOD 0x2550  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PERIOD_PERIOD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PERIOD_PERIOD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PATTERN 0x2554  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_INCR 0x2558  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_INCR_ADDR_FRAME_INCR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_INCR_ADDR_FRAME_INCR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BURST_LIMIT_CFG 0x255c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_MAX_BURST_LENGTH_MASK 0xf
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_MAX_BURST_LENGTH_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BURST_LIMIT_CFG_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG 0x2560  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG_SAMPLE_MODE_MASK 0x6
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG_SAMPLE_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL 0x2564  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_WORD_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_WORD_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_VAL 0x2568  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_VAL_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_VAL_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG 0x256c  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_0_SEL_MASK 0xff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_0_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_1_SEL_MASK 0xff00
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_STATUS_1_SEL_SHIFT 0x8
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_0 0x2570  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_0_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_0_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_1 0x2574  /*register offset*/
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_1_VAL_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_1_VAL_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_HW_VERSION 0x4000  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_HW_VERSION_STEP_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_HW_VERSION_STEP_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_HW_VERSION_REV_MASK 0xfff0000
#define IFE_LITE_IFE_LITE_CSID_HW_VERSION_REV_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_HW_VERSION_GEN_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_HW_VERSION_GEN_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_CFG0 0x4004  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CFG0_CGC_MODE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CFG0_CGC_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CFG0_PHY_BIST_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CFG0_PHY_BIST_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CFG0_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_CSID_CFG0_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_CSID_CTRL 0x4008  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CTRL_GLOBAL_HALT_CMD_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_CTRL_GLOBAL_HALT_CMD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CTRL_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_CSID_CTRL_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_CSID_RESET 0x400c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RESET_IFE_CLK_DOMAIN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RESET_IFE_CLK_DOMAIN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RESET_PHY_CLK_DOMAIN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RESET_PHY_CLK_DOMAIN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RESET_CSID_CLK_DOMAIN_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RESET_CSID_CLK_DOMAIN_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RESET_SW_REGS_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RESET_SW_REGS_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RESET_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_CSID_RESET_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_CSID_RST_STROBES 0x4010  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RST_STROBES_RST_STROBES_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RST_STROBES_RST_STROBES_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RST_STROBES_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RST_STROBES_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL 0x4014  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_UNUSED0_MASK 0xe
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_UNUSED0_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_TEST_BUS_SEL_MASK 0xffffff0
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_TEST_BUS_SEL_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_DOMAIN_SEL_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_DOMAIN_SEL_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_STATUS 0x4020  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_STATUS_STATUS_VEC_MASK 0xfffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_STATUS_STATUS_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_STATUS_UNUSED0_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_STATUS_UNUSED0_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_MASK 0x4024  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_MASK_MASK_VEC_MASK 0xfffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_MASK_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_MASK_UNUSED0_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_MASK_UNUSED0_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_CLEAR 0x4028  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_CLEAR_CLEAR_VEC_MASK 0xfffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_CLEAR_CLEAR_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_CLEAR_UNUSED0_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_CLEAR_UNUSED0_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_SET 0x402c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_SET_SET_VEC_MASK 0xfffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_SET_SET_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_SET_UNUSED0_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_SET_UNUSED0_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_RDI0_IRQ_STATUS 0x4030  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_STATUS_STATUS_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_STATUS_STATUS_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_STATUS_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_STATUS_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI0_IRQ_MASK 0x4034  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_MASK_MASK_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_MASK_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_MASK_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_MASK_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI0_IRQ_CLEAR 0x4038  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_CLEAR_CLEAR_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_CLEAR_CLEAR_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_CLEAR_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_CLEAR_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SET 0x403c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SET_SET_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SET_SET_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SET_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SET_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI1_IRQ_STATUS 0x4040  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_STATUS_STATUS_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_STATUS_STATUS_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_STATUS_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_STATUS_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI1_IRQ_MASK 0x4044  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_MASK_MASK_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_MASK_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_MASK_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_MASK_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI1_IRQ_CLEAR 0x4048  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_CLEAR_CLEAR_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_CLEAR_CLEAR_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_CLEAR_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_CLEAR_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SET 0x404c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SET_SET_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SET_SET_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SET_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SET_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI2_IRQ_STATUS 0x4050  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_STATUS_STATUS_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_STATUS_STATUS_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_STATUS_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_STATUS_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI2_IRQ_MASK 0x4054  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_MASK_MASK_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_MASK_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_MASK_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_MASK_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI2_IRQ_CLEAR 0x4058  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_CLEAR_CLEAR_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_CLEAR_CLEAR_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_CLEAR_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_CLEAR_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SET 0x405c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SET_SET_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SET_SET_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SET_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SET_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI3_IRQ_STATUS 0x4060  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_STATUS_STATUS_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_STATUS_STATUS_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_STATUS_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_STATUS_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI3_IRQ_MASK 0x4064  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_MASK_MASK_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_MASK_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_MASK_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_MASK_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI3_IRQ_CLEAR 0x4068  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_CLEAR_CLEAR_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_CLEAR_CLEAR_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_CLEAR_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_CLEAR_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SET 0x406c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SET_SET_VEC_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SET_SET_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SET_UNUSED0_MASK 0xffff8000
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SET_UNUSED0_SHIFT 0xf

#define regIFE_LITE_IFE_LITE_CSID_TOP_IRQ_STATUS 0x4070  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_STATUS_STATUS_VEC_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_STATUS_STATUS_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_STATUS_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_STATUS_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_TOP_IRQ_MASK 0x4074  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_MASK_MASK_VEC_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_MASK_MASK_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_MASK_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_MASK_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_TOP_IRQ_CLEAR 0x4078  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_CLEAR_CLEAR_VEC_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_CLEAR_CLEAR_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_CLEAR_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_CLEAR_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_TOP_IRQ_SET 0x407c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_SET_SET_VEC_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_SET_SET_VEC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_SET_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_TOP_IRQ_SET_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_IRQ_CMD 0x4080  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_CLEAR_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_CLEAR_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_UNUSED0_MASK 0xe
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_UNUSED0_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_SET_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_SET_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_UNUSED1_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_IRQ_CMD_UNUSED1_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_SPARE 0x4090  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_SPARE_SPARE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_SPARE_SPARE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_SPARE_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_SPARE_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0 0x4100  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_NUM_ACTIVE_LANES_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_NUM_ACTIVE_LANES_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED0_MASK 0xc
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED0_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL0_INPUT_SEL_MASK 0x30
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL0_INPUT_SEL_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED1_MASK 0xc0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED1_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL1_INPUT_SEL_MASK 0x300
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL1_INPUT_SEL_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED2_MASK 0xc00
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED2_SHIFT 0xa
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL2_INPUT_SEL_MASK 0x3000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL2_INPUT_SEL_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED3_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED3_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL3_INPUT_SEL_MASK 0x30000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_DL3_INPUT_SEL_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED4_MASK 0xc0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED4_SHIFT 0x12
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_PHY_NUM_SEL_MASK 0x300000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_PHY_NUM_SEL_SHIFT 0x14
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED5_MASK 0xc00000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED5_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_PHY_TYPE_SEL_MASK 0x1000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_PHY_TYPE_SEL_SHIFT 0x18
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED6_MASK 0xfe000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_UNUSED6_SHIFT 0x19

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1 0x4104  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_PACKET_ECC_CORRECTION_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_DE_SCRAMBLE_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_DE_SCRAMBLE_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_VC_MODE_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_VC_MODE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_UNUSED0_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_UNUSED0_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_COMPLETE_STREAM_EN_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_COMPLETE_STREAM_EN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_COMPLETE_STREAM_FRAME_TIMING_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_COMPLETE_STREAM_FRAME_TIMING_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_MISR_EN_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_MISR_EN_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_CGC_MODE_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_CGC_MODE_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_UNUSED1_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_UNUSED1_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL 0x4108  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_LONG_PKT_CAPTURE_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_LONG_PKT_CAPTURE_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_SHORT_PKT_CAPTURE_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_SHORT_PKT_CAPTURE_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_CPHY_PKT_CAPTURE_EN_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_CPHY_PKT_CAPTURE_EN_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_UNUSED0_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_UNUSED0_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_LONG_PKT_CAPTURE_VC_DT_MASK 0x7ff0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_LONG_PKT_CAPTURE_VC_DT_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_SHORT_PKT_CAPTURE_VC_MASK 0xf8000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_SHORT_PKT_CAPTURE_VC_SHIFT 0xf
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_CPHY_PKT_CAPTURE_VC_DT_MASK 0x7ff00000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_CPHY_PKT_CAPTURE_VC_DT_SHIFT 0x14
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_UNUSED1_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL_UNUSED1_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_RST_STROBES 0x4110  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_RST_STROBES_RST_STROBES_MASK 0x3fff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_RST_STROBES_RST_STROBES_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_RST_STROBES_UNUSED0_MASK 0xffffc000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_RST_STROBES_UNUSED0_SHIFT 0xe

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG0 0x4114  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG0_LANE1_SEED_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG0_LANE1_SEED_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG0_LANE0_SEED_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG0_LANE0_SEED_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG1 0x4118  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG1_LANE3_SEED_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG1_LANE3_SEED_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG1_LANE2_SEED_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG1_LANE2_SEED_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0 0x4120  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_WC_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_WC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_UNUSED0_MASK 0xf8000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0_UNUSED0_SHIFT 0x1b

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_1 0x4124  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_1_ECC_MASK 0x3f
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_1_ECC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_1_UNUSED0_MASK 0xffffffc0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_1_UNUSED0_SHIFT 0x6

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0 0x4128  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_FRAME_LINE_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_FRAME_LINE_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_UNUSED0_MASK 0xf8000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0_UNUSED0_SHIFT 0x1b

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_1 0x412c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_1_ECC_MASK 0x3f
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_1_ECC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_1_UNUSED0_MASK 0xffffffc0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_1_UNUSED0_SHIFT 0x6

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0 0x4130  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_WC_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_WC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_UNUSED0_MASK 0xf8000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0_UNUSED0_SHIFT 0x1b

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_1 0x4134  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_1_ECC_MASK 0x3f
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_1_ECC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_1_UNUSED0_MASK 0xffffffc0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_1_UNUSED0_SHIFT 0x6

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_FTR 0x4138  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_FTR_EXPECTED_CRC_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_FTR_EXPECTED_CRC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_FTR_CALCULATED_CRC_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_FTR_CALCULATED_CRC_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR 0x413c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_WC_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_WC_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_UNUSED0_MASK 0xf8000000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR_UNUSED0_SHIFT 0x1b

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE0_MISR 0x4150  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE0_MISR_MISR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE0_MISR_MISR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE1_MISR 0x4154  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE1_MISR_MISR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE1_MISR_MISR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE2_MISR 0x4158  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE2_MISR_MISR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE2_MISR_MISR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE3_MISR 0x415c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE3_MISR_MISR_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE3_MISR_MISR_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_PKTS_RCVD 0x4160  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_PKTS_RCVD_TOTAL_PKTS_RCVD_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_PKTS_RCVD_TOTAL_PKTS_RCVD_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_STATS_ECC 0x4164  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_STATS_ECC_TOTAL_RECOVERED_PKTS_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_STATS_ECC_TOTAL_RECOVERED_PKTS_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_STATS_ECC_TOTAL_UNRECOVERABLE_PKTS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_STATS_ECC_TOTAL_UNRECOVERABLE_PKTS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_CRC_ERRORS 0x4168  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_CRC_ERRORS_TOTAL_CRC_ERRORS_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_CRC_ERRORS_TOTAL_CRC_ERRORS_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_CRC_ERRORS_UNUSED0_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_CRC_ERRORS_UNUSED0_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_RDI0_CFG0 0x4200  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_BYTE_CNTR_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_BYTE_CNTR_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_FORMAT_MEASURE_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_FORMAT_MEASURE_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_TIMESTAMP_EN_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_TIMESTAMP_EN_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DROP_H_EN_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DROP_H_EN_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DROP_V_EN_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DROP_V_EN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CROP_H_EN_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CROP_H_EN_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CROP_V_EN_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CROP_V_EN_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_MISR_EN_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_MISR_EN_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CGC_MODE_MASK 0x100
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CGC_MODE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_PLAIN_ALIGNMENT_MASK 0x200
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_PLAIN_ALIGNMENT_SHIFT 0x9
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_PLAIN_FORMAT_MASK 0xc00
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_PLAIN_FORMAT_SHIFT 0xa
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DT_ID_MASK 0x18000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DT_ID_SHIFT 0x1b
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_EARLY_EOF_EN_MASK 0x20000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_EARLY_EOF_EN_SHIFT 0x1d
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_UNUSED0_MASK 0x40000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_UNUSED0_SHIFT 0x1e
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_EN_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_EN_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_RDI0_CFG1 0x4204  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG1_TIMESTAMP_STB_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG1_TIMESTAMP_STB_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG1_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_CSID_RDI0_CFG1_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_CSID_RDI0_CTRL 0x4208  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_CTRL_HALT_CMD_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI0_CTRL_HALT_CMD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_CTRL_HALT_MODE_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI0_CTRL_HALT_MODE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI0_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_RDI0_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PATTERN 0x420c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PERIOD 0x4210  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PATTERN 0x4214  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PERIOD 0x4218  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI0_RPP_HCROP 0x421c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_HCROP_START_PIXEL_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_HCROP_START_PIXEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_HCROP_END_PIXEL_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_HCROP_END_PIXEL_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP 0x4220  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_START_LINE_MASK 0x3fff
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_START_LINE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_UNUSED0_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_UNUSED0_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_END_LINE_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_END_LINE_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_UNUSED1_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP_UNUSED1_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PATTERN 0x4224  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PERIOD 0x4228  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PATTERN 0x422c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PERIOD 0x4230  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES 0x4240  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_CSID_CLK_RST_STB_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_CSID_CLK_RST_STB_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_IFE_CLK_RST_STB_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_IFE_CLK_RST_STB_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_MISR_RST_STB_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_MISR_RST_STB_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_FORMAT_MEASURE_RST_STB_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_FORMAT_MEASURE_RST_STB_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_TIMESTAMP_RST_STB_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_TIMESTAMP_RST_STB_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_FRAMEDROP_RST_STB_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_FRAMEDROP_RST_STB_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_BYTE_CNTR_RST_STB_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_BYTE_CNTR_RST_STB_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_CSID_RDI0_STATUS 0x4250  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_STATUS_HALT_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI0_STATUS_HALT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_STATUS_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_RDI0_STATUS_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL0 0x4254  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL0_MISR_VAL_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL0_MISR_VAL_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL1 0x4258  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL1_MISR_VAL_63_32_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL1_MISR_VAL_63_32_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL2 0x425c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL2_MISR_VAL_95_64_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL2_MISR_VAL_95_64_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL3 0x4260  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL3_MISR_VAL_127_96_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL3_MISR_VAL_127_96_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG0 0x4270  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG0_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG0_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1 0x4274  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1_NUM_PIX_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1_NUM_PIX_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1_NUM_LINES_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1_NUM_LINES_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0 0x4278  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0_PIX_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0_PIX_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0_LINE_COUNT_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0_LINE_COUNT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1 0x427c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_HBLANKING_MIN_MASK 0xfff
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_HBLANKING_MIN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_HBLANKING_MAX_MASK 0xfff0000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_HBLANKING_MAX_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_UNUSED1_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1_UNUSED1_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE2 0x4280  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE2_VBLANKING_COUNT_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE2_VBLANKING_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE2_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE2_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_SOF 0x4290  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_SOF 0x4294  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_SOF 0x4298  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_SOF 0x429c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_EOF 0x42a0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_EOF 0x42a4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_EOF 0x42a8  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_EOF 0x42ac  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PING 0x42e0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PING_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PING_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PONG 0x42e4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PONG_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PONG_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_CFG0 0x4300  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_BYTE_CNTR_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_BYTE_CNTR_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_FORMAT_MEASURE_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_FORMAT_MEASURE_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_TIMESTAMP_EN_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_TIMESTAMP_EN_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DROP_H_EN_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DROP_H_EN_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DROP_V_EN_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DROP_V_EN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CROP_H_EN_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CROP_H_EN_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CROP_V_EN_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CROP_V_EN_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_MISR_EN_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_MISR_EN_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CGC_MODE_MASK 0x100
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CGC_MODE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_PLAIN_ALIGNMENT_MASK 0x200
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_PLAIN_ALIGNMENT_SHIFT 0x9
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_PLAIN_FORMAT_MASK 0xc00
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_PLAIN_FORMAT_SHIFT 0xa
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DT_ID_MASK 0x18000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DT_ID_SHIFT 0x1b
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_EARLY_EOF_EN_MASK 0x20000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_EARLY_EOF_EN_SHIFT 0x1d
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_UNUSED0_MASK 0x40000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_UNUSED0_SHIFT 0x1e
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_EN_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_EN_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_RDI1_CFG1 0x4304  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG1_TIMESTAMP_STB_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG1_TIMESTAMP_STB_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG1_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_CSID_RDI1_CFG1_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_CSID_RDI1_CTRL 0x4308  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_CTRL_HALT_CMD_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI1_CTRL_HALT_CMD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_CTRL_HALT_MODE_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI1_CTRL_HALT_MODE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI1_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_RDI1_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PATTERN 0x430c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PERIOD 0x4310  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PATTERN 0x4314  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PERIOD 0x4318  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI1_RPP_HCROP 0x431c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_HCROP_START_PIXEL_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_HCROP_START_PIXEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_HCROP_END_PIXEL_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_HCROP_END_PIXEL_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP 0x4320  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_START_LINE_MASK 0x3fff
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_START_LINE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_UNUSED0_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_UNUSED0_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_END_LINE_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_END_LINE_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_UNUSED1_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP_UNUSED1_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PATTERN 0x4324  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PERIOD 0x4328  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PATTERN 0x432c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PERIOD 0x4330  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES 0x4340  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_CSID_CLK_RST_STB_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_CSID_CLK_RST_STB_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_IFE_CLK_RST_STB_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_IFE_CLK_RST_STB_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_MISR_RST_STB_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_MISR_RST_STB_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_FORMAT_MEASURE_RST_STB_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_FORMAT_MEASURE_RST_STB_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_TIMESTAMP_RST_STB_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_TIMESTAMP_RST_STB_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_FRAMEDROP_RST_STB_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_FRAMEDROP_RST_STB_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_BYTE_CNTR_RST_STB_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_BYTE_CNTR_RST_STB_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_CSID_RDI1_STATUS 0x4350  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_STATUS_HALT_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI1_STATUS_HALT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_STATUS_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_RDI1_STATUS_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL0 0x4354  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL0_MISR_VAL_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL0_MISR_VAL_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL1 0x4358  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL1_MISR_VAL_63_32_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL1_MISR_VAL_63_32_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL2 0x435c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL2_MISR_VAL_95_64_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL2_MISR_VAL_95_64_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL3 0x4360  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL3_MISR_VAL_127_96_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL3_MISR_VAL_127_96_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG0 0x4370  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG0_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG0_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1 0x4374  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1_NUM_PIX_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1_NUM_PIX_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1_NUM_LINES_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1_NUM_LINES_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0 0x4378  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0_PIX_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0_PIX_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0_LINE_COUNT_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0_LINE_COUNT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1 0x437c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_HBLANKING_MIN_MASK 0xfff
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_HBLANKING_MIN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_HBLANKING_MAX_MASK 0xfff0000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_HBLANKING_MAX_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_UNUSED1_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1_UNUSED1_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE2 0x4380  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE2_VBLANKING_COUNT_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE2_VBLANKING_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE2_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE2_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_SOF 0x4390  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_SOF 0x4394  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_SOF 0x4398  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_SOF 0x439c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_EOF 0x43a0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_EOF 0x43a4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_EOF 0x43a8  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_EOF 0x43ac  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PING 0x43e0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PING_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PING_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PONG 0x43e4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PONG_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PONG_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_CFG0 0x4400  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_BYTE_CNTR_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_BYTE_CNTR_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_FORMAT_MEASURE_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_FORMAT_MEASURE_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_TIMESTAMP_EN_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_TIMESTAMP_EN_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DROP_H_EN_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DROP_H_EN_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DROP_V_EN_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DROP_V_EN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CROP_H_EN_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CROP_H_EN_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CROP_V_EN_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CROP_V_EN_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_MISR_EN_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_MISR_EN_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CGC_MODE_MASK 0x100
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CGC_MODE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_PLAIN_ALIGNMENT_MASK 0x200
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_PLAIN_ALIGNMENT_SHIFT 0x9
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_PLAIN_FORMAT_MASK 0xc00
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_PLAIN_FORMAT_SHIFT 0xa
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DT_ID_MASK 0x18000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DT_ID_SHIFT 0x1b
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_EARLY_EOF_EN_MASK 0x20000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_EARLY_EOF_EN_SHIFT 0x1d
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_UNUSED0_MASK 0x40000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_UNUSED0_SHIFT 0x1e
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_EN_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_EN_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_RDI2_CFG1 0x4404  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG1_TIMESTAMP_STB_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG1_TIMESTAMP_STB_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG1_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_CSID_RDI2_CFG1_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_CSID_RDI2_CTRL 0x4408  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_CTRL_HALT_CMD_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI2_CTRL_HALT_CMD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_CTRL_HALT_MODE_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI2_CTRL_HALT_MODE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI2_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_RDI2_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PATTERN 0x440c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PERIOD 0x4410  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PATTERN 0x4414  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PERIOD 0x4418  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI2_RPP_HCROP 0x441c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_HCROP_START_PIXEL_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_HCROP_START_PIXEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_HCROP_END_PIXEL_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_HCROP_END_PIXEL_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP 0x4420  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_START_LINE_MASK 0x3fff
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_START_LINE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_UNUSED0_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_UNUSED0_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_END_LINE_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_END_LINE_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_UNUSED1_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP_UNUSED1_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PATTERN 0x4424  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PERIOD 0x4428  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PATTERN 0x442c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PERIOD 0x4430  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION 0x4434  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_COMPONENT_SWAP_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_COMPONENT_SWAP_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_ROUNDING_MODE_MASK 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_ROUNDING_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_EN_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_EN_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES 0x4440  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_CSID_CLK_RST_STB_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_CSID_CLK_RST_STB_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_IFE_CLK_RST_STB_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_IFE_CLK_RST_STB_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_MISR_RST_STB_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_MISR_RST_STB_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_FORMAT_MEASURE_RST_STB_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_FORMAT_MEASURE_RST_STB_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_TIMESTAMP_RST_STB_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_TIMESTAMP_RST_STB_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_FRAMEDROP_RST_STB_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_FRAMEDROP_RST_STB_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_BYTE_CNTR_RST_STB_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_BYTE_CNTR_RST_STB_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_CSID_RDI2_STATUS 0x4450  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_STATUS_HALT_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI2_STATUS_HALT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_STATUS_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_RDI2_STATUS_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL0 0x4454  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL0_MISR_VAL_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL0_MISR_VAL_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL1 0x4458  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL1_MISR_VAL_63_32_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL1_MISR_VAL_63_32_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL2 0x445c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL2_MISR_VAL_95_64_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL2_MISR_VAL_95_64_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL3 0x4460  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL3_MISR_VAL_127_96_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL3_MISR_VAL_127_96_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG0 0x4470  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG0_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG0_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1 0x4474  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1_NUM_PIX_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1_NUM_PIX_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1_NUM_LINES_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1_NUM_LINES_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0 0x4478  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0_PIX_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0_PIX_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0_LINE_COUNT_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0_LINE_COUNT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1 0x447c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_HBLANKING_MIN_MASK 0xfff
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_HBLANKING_MIN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_HBLANKING_MAX_MASK 0xfff0000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_HBLANKING_MAX_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_UNUSED1_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1_UNUSED1_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE2 0x4480  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE2_VBLANKING_COUNT_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE2_VBLANKING_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE2_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE2_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_SOF 0x4490  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_SOF 0x4494  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_SOF 0x4498  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_SOF 0x449c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_EOF 0x44a0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_EOF 0x44a4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_EOF 0x44a8  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_EOF 0x44ac  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PING 0x44e0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PING_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PING_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PONG 0x44e4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PONG_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PONG_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_CFG0 0x4500  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_BYTE_CNTR_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_BYTE_CNTR_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_FORMAT_MEASURE_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_FORMAT_MEASURE_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_TIMESTAMP_EN_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_TIMESTAMP_EN_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DROP_H_EN_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DROP_H_EN_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DROP_V_EN_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DROP_V_EN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CROP_H_EN_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CROP_H_EN_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CROP_V_EN_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CROP_V_EN_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_MISR_EN_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_MISR_EN_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CGC_MODE_MASK 0x100
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CGC_MODE_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_PLAIN_ALIGNMENT_MASK 0x200
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_PLAIN_ALIGNMENT_SHIFT 0x9
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_PLAIN_FORMAT_MASK 0xc00
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_PLAIN_FORMAT_SHIFT 0xa
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DT_MASK 0x3f0000
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_VC_MASK 0x7c00000
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_VC_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DT_ID_MASK 0x18000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DT_ID_SHIFT 0x1b
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_EARLY_EOF_EN_MASK 0x20000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_EARLY_EOF_EN_SHIFT 0x1d
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_UNUSED0_MASK 0x40000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_UNUSED0_SHIFT 0x1e
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_EN_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_EN_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_RDI3_CFG1 0x4504  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG1_TIMESTAMP_STB_SEL_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG1_TIMESTAMP_STB_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG1_UNUSED0_MASK 0xfffffffc
#define IFE_LITE_IFE_LITE_CSID_RDI3_CFG1_UNUSED0_SHIFT 0x2

#define regIFE_LITE_IFE_LITE_CSID_RDI3_CTRL 0x4508  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_CTRL_HALT_CMD_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI3_CTRL_HALT_CMD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_CTRL_HALT_MODE_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI3_CTRL_HALT_MODE_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI3_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_RDI3_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PATTERN 0x450c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PERIOD 0x4510  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PATTERN 0x4514  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PERIOD 0x4518  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI3_RPP_HCROP 0x451c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_HCROP_START_PIXEL_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_HCROP_START_PIXEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_HCROP_END_PIXEL_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_HCROP_END_PIXEL_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP 0x4520  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_START_LINE_MASK 0x3fff
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_START_LINE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_UNUSED0_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_UNUSED0_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_END_LINE_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_END_LINE_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_UNUSED1_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP_UNUSED1_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PATTERN 0x4524  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PERIOD 0x4528  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PATTERN 0x452c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PATTERN_PATTERN_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PATTERN_PATTERN_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PERIOD 0x4530  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PERIOD_PERIOD_MASK 0x1f
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PERIOD_PERIOD_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PERIOD_UNUSED0_MASK 0xffffffe0
#define IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PERIOD_UNUSED0_SHIFT 0x5

#define regIFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION 0x4534  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_COMPONENT_SWAP_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_COMPONENT_SWAP_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_ROUNDING_MODE_MASK 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_ROUNDING_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_EN_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_EN_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES 0x4540  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_CSID_CLK_RST_STB_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_CSID_CLK_RST_STB_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_IFE_CLK_RST_STB_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_IFE_CLK_RST_STB_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_MISR_RST_STB_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_MISR_RST_STB_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_FORMAT_MEASURE_RST_STB_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_FORMAT_MEASURE_RST_STB_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_TIMESTAMP_RST_STB_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_TIMESTAMP_RST_STB_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_FRAMEDROP_RST_STB_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_FRAMEDROP_RST_STB_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_IRQ_SUBSAMPLE_RST_STB_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_BYTE_CNTR_RST_STB_MASK 0x80
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_BYTE_CNTR_RST_STB_SHIFT 0x7
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_UNUSED0_MASK 0xffffff00
#define IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES_UNUSED0_SHIFT 0x8

#define regIFE_LITE_IFE_LITE_CSID_RDI3_STATUS 0x4550  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_STATUS_HALT_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_RDI3_STATUS_HALT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_STATUS_UNUSED0_MASK 0xfffffffe
#define IFE_LITE_IFE_LITE_CSID_RDI3_STATUS_UNUSED0_SHIFT 0x1

#define regIFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL0 0x4554  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL0_MISR_VAL_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL0_MISR_VAL_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL1 0x4558  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL1_MISR_VAL_63_32_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL1_MISR_VAL_63_32_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL2 0x455c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL2_MISR_VAL_95_64_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL2_MISR_VAL_95_64_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL3 0x4560  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL3_MISR_VAL_127_96_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL3_MISR_VAL_127_96_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG0 0x4570  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG0_COUNTER_ENABLES_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG0_UNUSED0_MASK 0xfffffff0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG0_UNUSED0_SHIFT 0x4

#define regIFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1 0x4574  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1_NUM_PIX_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1_NUM_PIX_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1_NUM_LINES_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1_NUM_LINES_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0 0x4578  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0_PIX_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0_PIX_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0_LINE_COUNT_MASK 0x3fff0000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0_LINE_COUNT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0_UNUSED0_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0_UNUSED0_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1 0x457c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_HBLANKING_MIN_MASK 0xfff
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_HBLANKING_MIN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_HBLANKING_MAX_MASK 0xfff0000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_HBLANKING_MAX_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_UNUSED1_MASK 0xf0000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1_UNUSED1_SHIFT 0x1c

#define regIFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE2 0x4580  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE2_VBLANKING_COUNT_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE2_VBLANKING_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE2_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE2_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_SOF 0x4590  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_SOF 0x4594  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_SOF 0x4598  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_SOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_SOF 0x459c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_SOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_SOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_SOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_EOF 0x45a0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_EOF 0x45a4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_EOF 0x45a8  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_EOF_TIMESTAMP_31_0_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_EOF 0x45ac  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_EOF_TIMESTAMP_55_32_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_EOF_UNUSED0_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_EOF_UNUSED0_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PING 0x45e0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PING_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PING_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PONG 0x45e4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PONG_BYTE_COUNT_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PONG_BYTE_COUNT_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_TPG_CTRL 0x4600  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_TEST_EN_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_TEST_EN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FS_PKT_EN_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FS_PKT_EN_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FE_PKT_EN_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FE_PKT_EN_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED0_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED0_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_NUM_ACTIVE_LANES_MASK 0x30
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_NUM_ACTIVE_LANES_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED1_MASK 0xc0
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED1_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_CYCLES_BETWEEN_PKTS_MASK 0x3ff00
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_CYCLES_BETWEEN_PKTS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED2_MASK 0xc0000
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED2_SHIFT 0x12
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_NUM_TRAIL_BYTES_MASK 0x3ff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_NUM_TRAIL_BYTES_SHIFT 0x14
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED3_MASK 0xc0000000
#define IFE_LITE_IFE_LITE_CSID_TPG_CTRL_UNUSED3_SHIFT 0x1e

#define regIFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0 0x4604  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_VC_NUM_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_VC_NUM_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_ACTIVE_DTS_MASK 0x300
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_ACTIVE_DTS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_LINE_INTERLEAVING_MODE_MASK 0xc00
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_LINE_INTERLEAVING_MODE_SHIFT 0xa
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_UNUSED1_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_UNUSED1_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_FRAMES_MASK 0xff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_FRAMES_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_UNUSED2_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_UNUSED2_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1 0x4608  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_H_BLANKING_COUNT_MASK 0x7ff
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_H_BLANKING_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_UNUSED0_MASK 0x800
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_UNUSED0_SHIFT 0xb
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_V_BLANKING_COUNT_MASK 0x3ff000
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_V_BLANKING_COUNT_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_UNUSED1_MASK 0xc00000
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_UNUSED1_SHIFT 0x16
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_V_BLANK_FRAME_WIDTH_SEL_MASK 0x3000000
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_V_BLANK_FRAME_WIDTH_SEL_SHIFT 0x18
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_UNUSED2_MASK 0xfc000000
#define IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1_UNUSED2_SHIFT 0x1a

#define regIFE_LITE_IFE_LITE_CSID_TPG_LFSR_SEED 0x460c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_LFSR_SEED_SEED_MASK 0xffffffff
#define IFE_LITE_IFE_LITE_CSID_TPG_LFSR_SEED_SEED_SHIFT 0x0

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0 0x4610  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_FRAME_HEIGHT_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_FRAME_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_UNUSED0_MASK 0x8000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_UNUSED0_SHIFT 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_FRAME_WIDTH_MASK 0x7fff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_FRAME_WIDTH_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_UNUSED1_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0_UNUSED1_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1 0x4614  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_DATA_TYPE_MASK 0x3f
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_DATA_TYPE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_UNUSED0_MASK 0xc0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_UNUSED0_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_ECC_XOR_MASK_MASK 0x3f00
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_ECC_XOR_MASK_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_UNUSED1_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_UNUSED1_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_CRC_XOR_MASK_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1_CRC_XOR_MASK_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2 0x4618  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_PAYLOAD_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_PAYLOAD_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_USER_SPECIFIED_PAYLOAD_MASK 0xff0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_USER_SPECIFIED_PAYLOAD_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_ENCODE_FORMAT_MASK 0xf0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_ENCODE_FORMAT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_UNUSED1_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2_UNUSED1_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0 0x461c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_FRAME_HEIGHT_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_FRAME_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_UNUSED0_MASK 0x8000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_UNUSED0_SHIFT 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_FRAME_WIDTH_MASK 0x7fff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_FRAME_WIDTH_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_UNUSED1_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0_UNUSED1_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1 0x4620  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_DATA_TYPE_MASK 0x3f
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_DATA_TYPE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_UNUSED0_MASK 0xc0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_UNUSED0_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_ECC_XOR_MASK_MASK 0x3f00
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_ECC_XOR_MASK_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_UNUSED1_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_UNUSED1_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_CRC_XOR_MASK_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1_CRC_XOR_MASK_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2 0x4624  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_PAYLOAD_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_PAYLOAD_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_USER_SPECIFIED_PAYLOAD_MASK 0xff0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_USER_SPECIFIED_PAYLOAD_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_ENCODE_FORMAT_MASK 0xf0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_ENCODE_FORMAT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_UNUSED1_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2_UNUSED1_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0 0x4628  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_FRAME_HEIGHT_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_FRAME_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_UNUSED0_MASK 0x8000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_UNUSED0_SHIFT 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_FRAME_WIDTH_MASK 0x7fff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_FRAME_WIDTH_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_UNUSED1_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0_UNUSED1_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1 0x462c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_DATA_TYPE_MASK 0x3f
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_DATA_TYPE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_UNUSED0_MASK 0xc0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_UNUSED0_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_ECC_XOR_MASK_MASK 0x3f00
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_ECC_XOR_MASK_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_UNUSED1_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_UNUSED1_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_CRC_XOR_MASK_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1_CRC_XOR_MASK_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2 0x4630  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_PAYLOAD_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_PAYLOAD_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_USER_SPECIFIED_PAYLOAD_MASK 0xff0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_USER_SPECIFIED_PAYLOAD_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_ENCODE_FORMAT_MASK 0xf0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_ENCODE_FORMAT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_UNUSED1_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2_UNUSED1_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0 0x4634  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_FRAME_HEIGHT_MASK 0x7fff
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_FRAME_HEIGHT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_UNUSED0_MASK 0x8000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_UNUSED0_SHIFT 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_FRAME_WIDTH_MASK 0x7fff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_FRAME_WIDTH_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_UNUSED1_MASK 0x80000000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0_UNUSED1_SHIFT 0x1f

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1 0x4638  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_DATA_TYPE_MASK 0x3f
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_DATA_TYPE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_UNUSED0_MASK 0xc0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_UNUSED0_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_ECC_XOR_MASK_MASK 0x3f00
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_ECC_XOR_MASK_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_UNUSED1_MASK 0xc000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_UNUSED1_SHIFT 0xe
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_CRC_XOR_MASK_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1_CRC_XOR_MASK_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2 0x463c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_PAYLOAD_MODE_MASK 0xf
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_PAYLOAD_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_USER_SPECIFIED_PAYLOAD_MASK 0xff0
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_USER_SPECIFIED_PAYLOAD_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_UNUSED0_MASK 0xf000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_UNUSED0_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_ENCODE_FORMAT_MASK 0xf0000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_ENCODE_FORMAT_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_UNUSED1_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2_UNUSED1_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG 0x4640  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNICOLOR_BAR_SEL_MASK 0x7
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNICOLOR_BAR_SEL_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNUSED0_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNUSED0_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNICOLOR_BAR_EN_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNICOLOR_BAR_EN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_SPLIT_EN_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_SPLIT_EN_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNUSED1_MASK 0xc0
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNUSED1_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_ROTATE_PERIOD_MASK 0x3f00
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_ROTATE_PERIOD_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNUSED2_MASK 0xffffc000
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG_UNUSED2_SHIFT 0xe

#define regIFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG 0x4644  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG_MODE_MASK 0x3
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG_PATTERN_SEL_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG_PATTERN_SEL_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG 0x4648  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_PIX_PATTERN_MASK 0x7
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_PIX_PATTERN_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_UNUSED0_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_UNUSED0_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_GAIN_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_GAIN_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_NUM_NOISE_BITS_MASK 0xf00
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_NUM_NOISE_BITS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_NOISE_EN_MASK 0x1000
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_NOISE_EN_SHIFT 0xc
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_UNUSED1_MASK 0xffffe000
#define IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG_UNUSED1_SHIFT 0xd

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN0_CFG 0x4650  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_CFG_MODE_MASK 0x7
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X0 0x4654  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X0_X0_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X0_X0_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X0_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X0_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X1 0x4658  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X1_X1_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X1_X1_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X1_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X1_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X2 0x465c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X2_X2_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X2_X2_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X2_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X2_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN0_XY 0x4660  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_XY_XY_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_XY_XY_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_XY_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_XY_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y1 0x4664  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y1_Y1_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y1_Y1_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y1_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y1_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y2 0x4668  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y2_Y2_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y2_Y2_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y2_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y2_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN1_CFG 0x4670  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_CFG_MODE_MASK 0x7
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X0 0x4674  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X0_X0_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X0_X0_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X0_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X0_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X1 0x4678  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X1_X1_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X1_X1_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X1_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X1_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X2 0x467c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X2_X2_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X2_X2_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X2_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X2_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN1_XY 0x4680  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_XY_XY_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_XY_XY_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_XY_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_XY_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y1 0x4684  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y1_Y1_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y1_Y1_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y1_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y1_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y2 0x4688  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y2_Y2_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y2_Y2_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y2_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y2_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN2_CFG 0x4690  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_CFG_MODE_MASK 0x7
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_CFG_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_CFG_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_CFG_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X0 0x4694  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X0_X0_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X0_X0_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X0_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X0_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X1 0x4698  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X1_X1_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X1_X1_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X1_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X1_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X2 0x469c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X2_X2_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X2_X2_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X2_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X2_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN2_XY 0x46a0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_XY_XY_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_XY_XY_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_XY_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_XY_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y1 0x46a4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y1_Y1_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y1_Y1_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y1_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y1_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y2 0x46a8  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y2_Y2_MASK 0xfffff
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y2_Y2_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y2_UNUSED0_MASK 0xfff00000
#define IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y2_UNUSED0_SHIFT 0x14

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0 0x4900  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0_SEED_DATA_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0_SEED_DATA_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0_UNUSED0_MASK 0xff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0_UNUSED0_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0_POLY_SEL_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0_POLY_SEL_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG1 0x4904  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG1_WORD_COUNT_INIT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG1_WORD_COUNT_INIT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG1_PATTERN_HEADER_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG1_PATTERN_HEADER_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2 0x4908  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_CHECKER_CROSS8_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_CHECKER_CROSS8_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_CHECKER_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_CHECKER_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_CHECKER_INVERT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_CHECKER_INVERT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL 0x490c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_CHECKER_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_CHECKER_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_CHECKER_CAPTURE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_CHECKER_CAPTURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_CLR_ERROR_COUNT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_CLR_ERROR_COUNT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS0 0x4910  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS0_ERROR_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS0_ERROR_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS0_WORD_COUNT_STATUS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS0_WORD_COUNT_STATUS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1 0x4914  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_ERROR_FLAG_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_ERROR_FLAG_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_SEED_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_SEED_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_ZERO_LFSR_FLAG_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_ZERO_LFSR_FLAG_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_CHECKER_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_CHECKER_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_CHECKER_STATUS_MASK 0x700
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_CHECKER_STATUS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_UNUSED1_MASK 0xfffff800
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1_UNUSED1_SHIFT 0xb

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0 0x4920  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0_SEED_DATA_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0_SEED_DATA_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0_UNUSED0_MASK 0xff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0_UNUSED0_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0_POLY_SEL_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0_POLY_SEL_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG1 0x4924  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG1_WORD_COUNT_INIT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG1_WORD_COUNT_INIT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG1_PATTERN_HEADER_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG1_PATTERN_HEADER_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2 0x4928  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_CHECKER_CROSS8_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_CHECKER_CROSS8_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_CHECKER_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_CHECKER_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_CHECKER_INVERT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_CHECKER_INVERT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL 0x492c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_CHECKER_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_CHECKER_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_CHECKER_CAPTURE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_CHECKER_CAPTURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_CLR_ERROR_COUNT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_CLR_ERROR_COUNT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS0 0x4930  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS0_ERROR_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS0_ERROR_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS0_WORD_COUNT_STATUS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS0_WORD_COUNT_STATUS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1 0x4934  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_ERROR_FLAG_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_ERROR_FLAG_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_SEED_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_SEED_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_ZERO_LFSR_FLAG_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_ZERO_LFSR_FLAG_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_CHECKER_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_CHECKER_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_CHECKER_STATUS_MASK 0x700
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_CHECKER_STATUS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_UNUSED1_MASK 0xfffff800
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1_UNUSED1_SHIFT 0xb

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0 0x4940  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0_SEED_DATA_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0_SEED_DATA_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0_UNUSED0_MASK 0xff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0_UNUSED0_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0_POLY_SEL_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0_POLY_SEL_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG1 0x4944  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG1_WORD_COUNT_INIT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG1_WORD_COUNT_INIT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG1_PATTERN_HEADER_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG1_PATTERN_HEADER_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2 0x4948  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_CHECKER_CROSS8_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_CHECKER_CROSS8_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_CHECKER_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_CHECKER_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_CHECKER_INVERT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_CHECKER_INVERT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL 0x494c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_CHECKER_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_CHECKER_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_CHECKER_CAPTURE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_CHECKER_CAPTURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_CLR_ERROR_COUNT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_CLR_ERROR_COUNT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS0 0x4950  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS0_ERROR_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS0_ERROR_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS0_WORD_COUNT_STATUS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS0_WORD_COUNT_STATUS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1 0x4954  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_ERROR_FLAG_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_ERROR_FLAG_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_SEED_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_SEED_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_ZERO_LFSR_FLAG_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_ZERO_LFSR_FLAG_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_CHECKER_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_CHECKER_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_CHECKER_STATUS_MASK 0x700
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_CHECKER_STATUS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_UNUSED1_MASK 0xfffff800
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1_UNUSED1_SHIFT 0xb

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0 0x4960  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0_SEED_DATA_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0_SEED_DATA_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0_UNUSED0_MASK 0xff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0_UNUSED0_SHIFT 0x10
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0_POLY_SEL_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0_POLY_SEL_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG1 0x4964  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG1_WORD_COUNT_INIT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG1_WORD_COUNT_INIT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG1_PATTERN_HEADER_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG1_PATTERN_HEADER_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2 0x4968  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_CHECKER_CROSS8_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_CHECKER_CROSS8_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_CHECKER_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_CHECKER_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_CHECKER_INVERT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_CHECKER_INVERT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL 0x496c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_CHECKER_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_CHECKER_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_CHECKER_CAPTURE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_CHECKER_CAPTURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_CLR_ERROR_COUNT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_CLR_ERROR_COUNT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS0 0x4970  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS0_ERROR_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS0_ERROR_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS0_WORD_COUNT_STATUS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS0_WORD_COUNT_STATUS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1 0x4974  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_ERROR_FLAG_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_ERROR_FLAG_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_SEED_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_SEED_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_ZERO_LFSR_FLAG_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_ZERO_LFSR_FLAG_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_CHECKER_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_CHECKER_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_CHECKER_STATUS_MASK 0x700
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_CHECKER_STATUS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_UNUSED1_MASK 0xfffff800
#define IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1_UNUSED1_SHIFT 0xb

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG0 0x4980  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG0_SEED_DATA_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG0_SEED_DATA_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG0_POLY_SEL_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG0_POLY_SEL_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG1 0x4984  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG1_WORD_COUNT_INIT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG1_WORD_COUNT_INIT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG1_PATTERN_HEADER2_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG1_PATTERN_HEADER2_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2 0x4988  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_HEADER_MODE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_HEADER_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_DOUBLE_SYNC_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_DOUBLE_SYNC_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_SYNC_DETECTED_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_SYNC_DETECTED_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_SECOND_SYNC_FLAG_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_SECOND_SYNC_FLAG_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_POST_DETECTED_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_POST_DETECTED_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_CHECKER_CROSS16_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_CHECKER_CROSS16_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_CHECKER_MODE_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_CHECKER_MODE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_UNUSED0_MASK 0xffffff80
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2_UNUSED0_SHIFT 0x7

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL 0x498c  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_CHECKER_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_CHECKER_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_CHECKER_CAPTURE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_CHECKER_CAPTURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_CLR_ERROR_COUNT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_CLR_ERROR_COUNT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS0 0x4990  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS0_ERROR_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS0_ERROR_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS0_WORD_COUNT_STATUS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS0_WORD_COUNT_STATUS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1 0x4994  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_ERROR_FLAG_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_ERROR_FLAG_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_SEED_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_SEED_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_ZERO_LFSR_FLAG_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_ZERO_LFSR_FLAG_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_CHECKER_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_CHECKER_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_CHECKER_STATUS_MASK 0x700
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_CHECKER_STATUS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_UNUSED1_MASK 0xfffff800
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1_UNUSED1_SHIFT 0xb

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG0 0x49a0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG0_SEED_DATA_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG0_SEED_DATA_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG0_POLY_SEL_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG0_POLY_SEL_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG1 0x49a4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG1_WORD_COUNT_INIT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG1_WORD_COUNT_INIT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG1_PATTERN_HEADER2_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG1_PATTERN_HEADER2_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2 0x49a8  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_HEADER_MODE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_HEADER_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_DOUBLE_SYNC_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_DOUBLE_SYNC_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_SYNC_DETECTED_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_SYNC_DETECTED_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_SECOND_SYNC_FLAG_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_SECOND_SYNC_FLAG_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_POST_DETECTED_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_POST_DETECTED_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_CHECKER_CROSS16_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_CHECKER_CROSS16_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_CHECKER_MODE_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_CHECKER_MODE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_UNUSED0_MASK 0xffffff80
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2_UNUSED0_SHIFT 0x7

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL 0x49ac  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_CHECKER_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_CHECKER_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_CHECKER_CAPTURE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_CHECKER_CAPTURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_CLR_ERROR_COUNT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_CLR_ERROR_COUNT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS0 0x49b0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS0_ERROR_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS0_ERROR_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS0_WORD_COUNT_STATUS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS0_WORD_COUNT_STATUS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1 0x49b4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_ERROR_FLAG_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_ERROR_FLAG_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_SEED_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_SEED_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_ZERO_LFSR_FLAG_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_ZERO_LFSR_FLAG_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_CHECKER_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_CHECKER_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_CHECKER_STATUS_MASK 0x700
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_CHECKER_STATUS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_UNUSED1_MASK 0xfffff800
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1_UNUSED1_SHIFT 0xb

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG0 0x49c0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG0_SEED_DATA_MASK 0xffffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG0_SEED_DATA_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG0_POLY_SEL_MASK 0xff000000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG0_POLY_SEL_SHIFT 0x18

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG1 0x49c4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG1_WORD_COUNT_INIT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG1_WORD_COUNT_INIT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG1_PATTERN_HEADER2_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG1_PATTERN_HEADER2_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2 0x49c8  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_HEADER_MODE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_HEADER_MODE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_DOUBLE_SYNC_MODE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_DOUBLE_SYNC_MODE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_SYNC_DETECTED_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_SYNC_DETECTED_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_SECOND_SYNC_FLAG_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_SECOND_SYNC_FLAG_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_POST_DETECTED_MASK 0x10
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_POST_DETECTED_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_CHECKER_CROSS16_MASK 0x20
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_CHECKER_CROSS16_SHIFT 0x5
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_CHECKER_MODE_MASK 0x40
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_CHECKER_MODE_SHIFT 0x6
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_UNUSED0_MASK 0xffffff80
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2_UNUSED0_SHIFT 0x7

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL 0x49cc  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_CHECKER_ENABLE_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_CHECKER_ENABLE_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_CHECKER_CAPTURE_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_CHECKER_CAPTURE_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_CLR_ERROR_COUNT_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_CLR_ERROR_COUNT_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_UNUSED0_MASK 0xfffffff8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL_UNUSED0_SHIFT 0x3

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS0 0x49d0  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS0_ERROR_COUNT_MASK 0xffff
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS0_ERROR_COUNT_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS0_WORD_COUNT_STATUS_MASK 0xffff0000
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS0_WORD_COUNT_STATUS_SHIFT 0x10

#define regIFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1 0x49d4  /*register offset*/
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_ERROR_FLAG_MASK 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_ERROR_FLAG_SHIFT 0x0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_SEED_ERROR_MASK 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_SEED_ERROR_SHIFT 0x1
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_ZERO_LFSR_FLAG_MASK 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_ZERO_LFSR_FLAG_SHIFT 0x2
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_CHECKER_DONE_MASK 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_CHECKER_DONE_SHIFT 0x3
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_UNUSED0_MASK 0xf0
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_UNUSED0_SHIFT 0x4
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_CHECKER_STATUS_MASK 0x700
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_CHECKER_STATUS_SHIFT 0x8
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_UNUSED1_MASK 0xfffff800
#define IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1_UNUSED1_SHIFT 0xb

/*----------------------------------------------------------------------
        Register Data Structures
----------------------------------------------------------------------*/

typedef struct{
    unsigned  INCR_VERSION : 16; /* 15:0 */
    unsigned  MINOR_VERSION : 12; /* 27:16 */
    unsigned  MAJOR_VERSION : 4; /* 31:28 */
} _ife_lite_ife_lite_vfe_hw_version;

typedef union{
    _ife_lite_ife_lite_vfe_hw_version bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_HW_VERSION;

typedef struct{
    unsigned  BUS_FEATURE : 3; /* 2:0 */
    unsigned  THREE_D_FEATURE : 1; /* 3:3 */
    unsigned  UNUSED0 : 12; /* 15:4 */
    unsigned  MAIN_LINE_BUFFER_FEATURE : 13; /* 28:16 */
    unsigned  RDI_FEATURE : 2; /* 30:29 */
    unsigned  INPUT_FORMAT_FEATURE : 1; /* 31:31 */
} _ife_lite_ife_lite_vfe_hw_capability;

typedef union{
    _ife_lite_ife_lite_vfe_hw_capability bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_HW_CAPABILITY;

typedef struct{
    unsigned  PEDESTAL_FEATURE : 1; /* 0:0 */
    unsigned  BLACK_FEATURE : 1; /* 1:1 */
    unsigned  DEMUX_FEATURE : 1; /* 2:2 */
    unsigned  CHROMA_UPSAMPLE_FEATURE : 1; /* 3:3 */
    unsigned  HDR_RECON_FEATURE : 1; /* 4:4 */
    unsigned  HDR_MAC_FEATURE : 1; /* 5:5 */
    unsigned  BPC_FEATURE : 1; /* 6:6 */
    unsigned  ABF_FEATURE : 1; /* 7:7 */
    unsigned  ROLLOFF_FEATURE : 1; /* 8:8 */
    unsigned  GIC_FEATURE : 1; /* 9:9 */
    unsigned  DEMO_FEATURE : 2; /* 11:10 */
    unsigned  BLACK_LEVEL_FEATURE : 1; /* 12:12 */
    unsigned  PDAF_FEATURE : 1; /* 13:13 */
    unsigned  UNUSED0 : 18; /* 31:14 */
} _ife_lite_ife_lite_vfe_module_lens_feature;

typedef union{
    _ife_lite_ife_lite_vfe_module_lens_feature bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_MODULE_LENS_FEATURE;

typedef struct{
    unsigned  HDR_BE_FEATURE : 1; /* 0:0 */
    unsigned  HDR_BHIST_FEATURE : 1; /* 1:1 */
    unsigned  BAF_FEATURE : 1; /* 2:2 */
    unsigned  AWB_BG_FEATURE : 1; /* 3:3 */
    unsigned  SKIN_BHIST_FEATURE : 1; /* 4:4 */
    unsigned  RS_FEATURE : 1; /* 5:5 */
    unsigned  CS_FEATURE : 1; /* 6:6 */
    unsigned  IHIST_FEATURE : 1; /* 7:7 */
    unsigned  AEC_BG_FEATURE : 1; /* 8:8 */
    unsigned  UNUSED0 : 23; /* 31:9 */
} _ife_lite_ife_lite_vfe_module_stats_feature;

typedef union{
    _ife_lite_ife_lite_vfe_module_stats_feature bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_MODULE_STATS_FEATURE;

typedef struct{
    unsigned  CAC_SNR_FEATURE : 1; /* 0:0 */
    unsigned  COLOR_CORRECT_FEATURE : 1; /* 1:1 */
    unsigned  GTM_FEATURE : 1; /* 2:2 */
    unsigned  RGB_LUT_FEATURE : 1; /* 3:3 */
    unsigned  LTM_FEATURE : 1; /* 4:4 */
    unsigned  CHROMA_ENHAN_FEATURE : 1; /* 5:5 */
    unsigned  CHROMA_SUPPRESS_MCE_FEATURE : 1; /* 6:6 */
    unsigned  SKIN_ENHAN_FEATURE : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_vfe_module_color_feature;

typedef union{
    _ife_lite_ife_lite_vfe_module_color_feature bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_MODULE_COLOR_FEATURE;

typedef struct{
    unsigned  CST_FEATURE : 1; /* 0:0 */
    unsigned  UNUSED0 : 2; /* 2:1 */
    unsigned  SCALE_FEATURE : 3; /* 5:3 */
    unsigned  CROP_FEATURE : 3; /* 8:6 */
    unsigned  REALIGN_BUF_FEATURE : 1; /* 9:9 */
    unsigned  DS_4TO1_Y_1ST_FEATURE : 1; /* 10:10 */
    unsigned  DS_4TO1_Y_2ND_FEATURE : 1; /* 11:11 */
    unsigned  DS_4TO1_C_1ST_FEATURE : 1; /* 12:12 */
    unsigned  DS_4TO1_C_2ND_FEATURE : 1; /* 13:13 */
    unsigned  R2PD_1ST_FEATURE : 1; /* 14:14 */
    unsigned  R2PD_2ND_FEATURE : 1; /* 15:15 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _ife_lite_ife_lite_vfe_module_zoom_feature;

typedef union{
    _ife_lite_ife_lite_vfe_module_zoom_feature bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_MODULE_ZOOM_FEATURE;

typedef struct{
    unsigned  CORE_RESET : 1; /* 0:0 */
    unsigned  UNUSED0 : 1; /* 1:1 */
    unsigned  BUS_HW_RESET : 1; /* 2:2 */
    unsigned  BUS_SW_RESET : 1; /* 3:3 */
    unsigned  REGISTER_RESET : 1; /* 4:4 */
    unsigned  UNUSED1 : 4; /* 8:5 */
    unsigned  IDLE_CGC_RESET : 1; /* 9:9 */
    unsigned  RDI_0_RESET : 1; /* 10:10 */
    unsigned  RDI_1_RESET : 1; /* 11:11 */
    unsigned  RDI_2_RESET : 1; /* 12:12 */
    unsigned  RDI_3_RESET : 1; /* 13:13 */
    unsigned  UNUSED2 : 16; /* 29:14 */
    unsigned  VFE_DOMAIN_RESET : 1; /* 30:30 */
    unsigned  RESET_BYPASS : 1; /* 31:31 */
} _ife_lite_ife_lite_vfe_global_reset_cmd;

typedef union{
    _ife_lite_ife_lite_vfe_global_reset_cmd bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_GLOBAL_RESET_CMD;

typedef struct{
    unsigned  BUS_WR_IF_CGC_OVERRIDE : 1; /* 0:0 */
    unsigned  TESTGEN_CGC_OVERRIDE : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_vfe_module_bus_cgc_override;

typedef union{
    _ife_lite_ife_lite_vfe_module_bus_cgc_override bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_MODULE_BUS_CGC_OVERRIDE;

typedef struct{
    unsigned  UNUSED0 : 7; /* 6:0 */
    unsigned  CAMNOC_HALT_DIS : 1; /* 7:7 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _ife_lite_ife_lite_vfe_core_cfg;

typedef union{
    _ife_lite_ife_lite_vfe_core_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_CORE_CFG;

typedef struct{
    unsigned  GLOBAL_CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_vfe_irq_cmd;

typedef union{
    _ife_lite_ife_lite_vfe_irq_cmd bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_IRQ_CMD;

typedef struct{
    unsigned  MASK : 32; /* 31:0 */
} _ife_lite_ife_lite_vfe_irq_mask_0;

typedef union{
    _ife_lite_ife_lite_vfe_irq_mask_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_IRQ_MASK_0;

typedef struct{
    unsigned  MASK : 32; /* 31:0 */
} _ife_lite_ife_lite_vfe_irq_mask_1;

typedef union{
    _ife_lite_ife_lite_vfe_irq_mask_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_IRQ_MASK_1;

typedef struct{
    unsigned  CLEAR : 32; /* 31:0 */
} _ife_lite_ife_lite_vfe_irq_clear_0;

typedef union{
    _ife_lite_ife_lite_vfe_irq_clear_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_0;

typedef struct{
    unsigned  CLEAR : 32; /* 31:0 */
} _ife_lite_ife_lite_vfe_irq_clear_1;

typedef union{
    _ife_lite_ife_lite_vfe_irq_clear_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_IRQ_CLEAR_1;

typedef struct{
    unsigned  STATUS : 32; /* 31:0 */
} _ife_lite_ife_lite_vfe_irq_status_0;

typedef union{
    _ife_lite_ife_lite_vfe_irq_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_IRQ_STATUS_0;

typedef struct{
    unsigned  STATUS : 32; /* 31:0 */
} _ife_lite_ife_lite_vfe_irq_status_1;

typedef union{
    _ife_lite_ife_lite_vfe_irq_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_IRQ_STATUS_1;

typedef struct{
    unsigned  STATUS : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _ife_lite_ife_lite_vfe_violation_status;

typedef union{
    _ife_lite_ife_lite_vfe_violation_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_VIOLATION_STATUS;

typedef struct{
    unsigned  UPDATE : 1; /* 0:0 */
    unsigned  RDI0_UPDATE : 1; /* 1:1 */
    unsigned  RDI1_UPDATE : 1; /* 2:2 */
    unsigned  RDI2_UPDATE : 1; /* 3:3 */
    unsigned  RDI3_UPDATE : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_vfe_reg_update_cmd;

typedef union{
    _ife_lite_ife_lite_vfe_reg_update_cmd bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_REG_UPDATE_CMD;

typedef struct{
    unsigned  DIAG_EN : 1; /* 0:0 */
    unsigned  SENSOR_SEL : 3; /* 3:1 */
    unsigned  RDI3_FRM_CNT_EN : 1; /* 4:4 */
    unsigned  RDI0_FRM_CNT_EN : 1; /* 5:5 */
    unsigned  RDI1_FRM_CNT_EN : 1; /* 6:6 */
    unsigned  RDI2_FRM_CNT_EN : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_vfe_diag_cfg;

typedef union{
    _ife_lite_ife_lite_vfe_diag_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_DIAG_CFG;

typedef struct{
    unsigned  SENSOR_HBI : 14; /* 13:0 */
    unsigned  SENSOR_NEQ_HBI : 1; /* 14:14 */
    unsigned  SENSOR_HBI_MIN_ERROR : 1; /* 15:15 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_vfe_diag_sensor_status;

typedef union{
    _ife_lite_ife_lite_vfe_diag_sensor_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_STATUS;

typedef struct{
    unsigned  OUTPUT_SEL : 1; /* 0:0 */
    unsigned  EVENT_SITE_SEL : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_vfe_stm_cfg;

typedef union{
    _ife_lite_ife_lite_vfe_stm_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_STM_CFG;

typedef struct{
    unsigned  BUS_SEL : 4; /* 3:0 */
    unsigned  DOMAIN_SEL : 3; /* 6:4 */
    unsigned  TESTBUS_EN : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_vfe_testbus_sel;

typedef union{
    _ife_lite_ife_lite_vfe_testbus_sel bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL;

typedef struct{
    unsigned  PWR_ISO_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_vfe_pwr_iso_cfg;

typedef union{
    _ife_lite_ife_lite_vfe_pwr_iso_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_PWR_ISO_CFG;

typedef struct{
    unsigned  RDI3_FRM_CNT : 8; /* 7:0 */
    unsigned  RDI0_FRM_CNT : 8; /* 15:8 */
    unsigned  RDI1_FRM_CNT : 8; /* 23:16 */
    unsigned  RDI2_FRM_CNT : 8; /* 31:24 */
} _ife_lite_ife_lite_vfe_diag_sensor_frm_cnt_status;

typedef union{
    _ife_lite_ife_lite_vfe_diag_sensor_frm_cnt_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_DIAG_SENSOR_FRM_CNT_STATUS;

typedef struct{
    unsigned  SPARE : 32; /* 31:0 */
} _ife_lite_ife_lite_vfe_vfe_spare;

typedef union{
    _ife_lite_ife_lite_vfe_vfe_spare bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_VFE_VFE_SPARE;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _ife_lite_ife_lite_bus_wr_hw_version;

typedef union{
    _ife_lite_ife_lite_bus_wr_hw_version bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_HW_VERSION;

typedef struct{
    unsigned  FEATURE : 8; /* 7:0 */
    unsigned  LITE : 8; /* 15:8 */
    unsigned  UBWC : 8; /* 23:16 */
    unsigned  REG : 8; /* 31:24 */
} _ife_lite_ife_lite_bus_wr_hw_capability;

typedef union{
    _ife_lite_ife_lite_bus_wr_hw_capability bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_HW_CAPABILITY;

typedef struct{
    unsigned  SW_RESET : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_sw_reset;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_sw_reset bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_SW_RESET;

typedef struct{
    unsigned  CGC_OVERRIGE : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_cgc_override;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_cgc_override bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_CGC_OVERRIDE;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_composite_mask_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_composite_mask_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_0;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_composite_mask_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_composite_mask_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_1;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_composite_mask_2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_composite_mask_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_2;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_composite_mask_3;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_composite_mask_3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_3;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_composite_mask_4;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_composite_mask_4 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_4;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_composite_mask_5;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_composite_mask_5 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMPOSITE_MASK_5;

typedef struct{
    unsigned  INTRA_CLIENT_EN : 12; /* 11:0 */
    unsigned  UNUSED0 : 20; /* 31:12 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_CFG;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_0;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_1;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_2;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_3;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_3;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_4;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_4 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_4;

typedef struct{
    unsigned  MASK_VEC : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_5;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_master_composite_mask_5 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_MASTER_COMPOSITE_MASK_5;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_mask_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_mask_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 4; /* 3:0 */
    unsigned  UNUSED0 : 20; /* 23:4 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_mask_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_mask_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_1;

typedef struct{
    unsigned  DUAL_COMP0_BUF_DONE : 1; /* 0:0 */
    unsigned  DUAL_COMP1_BUF_DONE : 1; /* 1:1 */
    unsigned  DUAL_COMP2_BUF_DONE : 1; /* 2:2 */
    unsigned  DUAL_COMP3_BUF_DONE : 1; /* 3:3 */
    unsigned  DUAL_COMP4_BUF_DONE : 1; /* 4:4 */
    unsigned  DUAL_COMP5_BUF_DONE : 1; /* 5:5 */
    unsigned  DUAL_COMP_ERROR : 1; /* 6:6 */
    unsigned  DUAL_COMP_OVERWRITE : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_mask_2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_mask_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_MASK_2;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_clear_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_clear_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 4; /* 3:0 */
    unsigned  UNUSED0 : 20; /* 23:4 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_clear_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_clear_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_1;

typedef struct{
    unsigned  DUAL_COMP0_BUF_DONE : 1; /* 0:0 */
    unsigned  DUAL_COMP1_BUF_DONE : 1; /* 1:1 */
    unsigned  DUAL_COMP2_BUF_DONE : 1; /* 2:2 */
    unsigned  DUAL_COMP3_BUF_DONE : 1; /* 3:3 */
    unsigned  DUAL_COMP4_BUF_DONE : 1; /* 4:4 */
    unsigned  DUAL_COMP5_BUF_DONE : 1; /* 5:5 */
    unsigned  DUAL_COMP_ERROR : 1; /* 6:6 */
    unsigned  DUAL_COMP_OVERWRITE : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_clear_2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_clear_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CLEAR_2;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 4; /* 3:0 */
    unsigned  UNUSED0 : 20; /* 23:4 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_1;

typedef struct{
    unsigned  DUAL_COMP0_BUF_DONE : 1; /* 0:0 */
    unsigned  DUAL_COMP1_BUF_DONE : 1; /* 1:1 */
    unsigned  DUAL_COMP2_BUF_DONE : 1; /* 2:2 */
    unsigned  DUAL_COMP3_BUF_DONE : 1; /* 3:3 */
    unsigned  DUAL_COMP4_BUF_DONE : 1; /* 4:4 */
    unsigned  DUAL_COMP5_BUF_DONE : 1; /* 5:5 */
    unsigned  DUAL_COMP_ERROR : 1; /* 6:6 */
    unsigned  DUAL_COMP_OVERWRITE : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_status_2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_status_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_STATUS_2;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_cmd;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_cmd bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_CMD;

typedef struct{
    unsigned  CLIENT_COMP_IRQ_ERROR : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_comp_error_status;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_comp_error_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_ERROR_STATUS;

typedef struct{
    unsigned  CLIENT_COMP_OVERWRITE_ERROR : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_comp_overwrite_error_status;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_comp_overwrite_error_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_COMP_OVERWRITE_ERROR_STATUS;

typedef struct{
    unsigned  SLV0_COMP_IRQ_ERROR : 1; /* 0:0 */
    unsigned  SLV1_COMP_IRQ_ERROR : 1; /* 1:1 */
    unsigned  CLIENT_COMP_IRQ_ERROR : 4; /* 5:2 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_comp_error_status;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_comp_error_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_ERROR_STATUS;

typedef struct{
    unsigned  SLV0_COMP_OVERWRITE_ERROR : 1; /* 0:0 */
    unsigned  SLV1_COMP_OVERWRITE_ERROR : 1; /* 1:1 */
    unsigned  CLIENT_COMP_OVERWRITE_ERROR : 4; /* 5:2 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _ife_lite_ife_lite_bus_wr_input_if_dual_comp_overwrite_status;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_dual_comp_overwrite_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_DUAL_COMP_OVERWRITE_STATUS;

typedef struct{
    unsigned  MODE : 8; /* 7:0 */
    unsigned  INTRA_CLIENT_EN : 16; /* 23:8 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_CFG;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_frame_header;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_frame_header bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_FRAME_HEADER;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_no_sync;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_no_sync bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_NO_SYNC;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_0;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_1;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_2;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_3;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_3;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_4;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_4 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_4;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_5;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_5 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_5;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_6;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_6 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_6;

typedef struct{
    unsigned  EN : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_sync_7;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_sync_7 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_SYNC_7;

typedef struct{
    unsigned  FIFO_STATUS : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_input_if_addr_fifo_status;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_addr_fifo_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_ADDR_FIFO_STATUS;

typedef struct{
    unsigned  CFG0 : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG0;

typedef struct{
    unsigned  CFG1 : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG1;

typedef struct{
    unsigned  CFG2 : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG2;

typedef struct{
    unsigned  CFG3 : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg3;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG3;

typedef struct{
    unsigned  COMP_RESET_DONE : 1; /* 0:0 */
    unsigned  COMP_REG_UPDATE0_DONE : 1; /* 1:1 */
    unsigned  COMP_REG_UPDATE1_DONE : 1; /* 2:2 */
    unsigned  COMP_REG_UPDATE2_DONE : 1; /* 3:3 */
    unsigned  COMP_REG_UPDATE3_DONE : 1; /* 4:4 */
    unsigned  COMP0_BUF_DONE : 1; /* 5:5 */
    unsigned  COMP1_BUF_DONE : 1; /* 6:6 */
    unsigned  COMP2_BUF_DONE : 1; /* 7:7 */
    unsigned  COMP3_BUF_DONE : 1; /* 8:8 */
    unsigned  COMP4_BUF_DONE : 1; /* 9:9 */
    unsigned  COMP5_BUF_DONE : 1; /* 10:10 */
    unsigned  COMP_ERROR : 1; /* 11:11 */
    unsigned  COMP_OVERWRITE : 1; /* 12:12 */
    unsigned  OVERFLOW_ERROR : 1; /* 13:13 */
    unsigned  VIOLATION : 1; /* 14:14 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_set_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_set_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_0;

typedef struct{
    unsigned  WR_CLIENT_BUF_DONE : 4; /* 3:0 */
    unsigned  UNUSED0 : 20; /* 23:4 */
    unsigned  EARLY_DONE : 2; /* 25:24 */
    unsigned  UNUSED1 : 6; /* 31:26 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_set_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_set_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_1;

typedef struct{
    unsigned  DUAL_COMP0_BUF_DONE : 1; /* 0:0 */
    unsigned  DUAL_COMP1_BUF_DONE : 1; /* 1:1 */
    unsigned  DUAL_COMP2_BUF_DONE : 1; /* 2:2 */
    unsigned  DUAL_COMP3_BUF_DONE : 1; /* 3:3 */
    unsigned  DUAL_COMP4_BUF_DONE : 1; /* 4:4 */
    unsigned  DUAL_COMP5_BUF_DONE : 1; /* 5:5 */
    unsigned  DUAL_COMP_ERROR : 1; /* 6:6 */
    unsigned  DUAL_COMP_OVERWRITE : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_bus_wr_input_if_irq_set_2;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_irq_set_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_IRQ_SET_2;

typedef struct{
    unsigned  RESET : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_bus_wr_input_if_misr_reset;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_misr_reset bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_MISR_RESET;

typedef struct{
    unsigned  PWR_ISO_ENABLE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_bus_wr_pwr_iso_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_pwr_iso_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_PWR_ISO_CFG;

typedef struct{
    unsigned  CFG4 : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg4;

typedef union{
    _ife_lite_ife_lite_bus_wr_input_if_frame_header_cfg4 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_INPUT_IF_FRAME_HEADER_CFG4;

typedef struct{
    unsigned  TEST_BUS_EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_CLIENT_SEL : 5; /* 8:4 */
    unsigned  TEST_BUS_INTERNAL_SEL : 7; /* 15:9 */
    unsigned  UNUSED1 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_test_bus_ctrl;

typedef union{
    _ife_lite_ife_lite_bus_wr_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_TEST_BUS_CTRL;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_bus_wr_spare;

typedef union{
    _ife_lite_ife_lite_bus_wr_spare bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_SPARE;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_0_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_addr_frame_header;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_addr_frame_header bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_frame_header_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_addr_image;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_addr_image bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_addr_image_offset;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_addr_image_offset bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_buffer_width_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_0_buffer_height_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_bus_wr_client_0_packer_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_packer_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _ife_lite_ife_lite_bus_wr_client_0_wr_stride;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_wr_stride bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_irq_subsample_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_irq_subsample_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_framedrop_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_framedrop_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_framedrop_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_framedrop_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_FRAMEDROP_CFG_PATTERN;

typedef struct{
    unsigned  ADDR_FRAME_INCR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_addr_frame_incr;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_addr_frame_incr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_ADDR_FRAME_INCR;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_client_0_burst_limit_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_0_misr_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_misr_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_bus_wr_client_0_misr_rd_word_sel;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_misr_val;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_misr_val bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_0_debug_status_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_debug_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_debug_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_0_debug_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_0_debug_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_0_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_1_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_addr_frame_header;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_addr_frame_header bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_frame_header_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_addr_image;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_addr_image bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_addr_image_offset;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_addr_image_offset bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_buffer_width_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_1_buffer_height_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_bus_wr_client_1_packer_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_packer_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _ife_lite_ife_lite_bus_wr_client_1_wr_stride;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_wr_stride bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_irq_subsample_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_irq_subsample_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_framedrop_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_framedrop_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_framedrop_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_framedrop_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_FRAMEDROP_CFG_PATTERN;

typedef struct{
    unsigned  ADDR_FRAME_INCR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_addr_frame_incr;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_addr_frame_incr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_ADDR_FRAME_INCR;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_client_1_burst_limit_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_1_misr_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_misr_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_bus_wr_client_1_misr_rd_word_sel;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_misr_val;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_misr_val bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_1_debug_status_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_debug_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_debug_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_1_debug_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_1_debug_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_1_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_2_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_addr_frame_header;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_addr_frame_header bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_frame_header_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_addr_image;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_addr_image bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_addr_image_offset;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_addr_image_offset bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_buffer_width_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_2_buffer_height_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_bus_wr_client_2_packer_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_packer_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _ife_lite_ife_lite_bus_wr_client_2_wr_stride;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_wr_stride bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_irq_subsample_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_irq_subsample_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_framedrop_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_framedrop_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_framedrop_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_framedrop_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_FRAMEDROP_CFG_PATTERN;

typedef struct{
    unsigned  ADDR_FRAME_INCR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_addr_frame_incr;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_addr_frame_incr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_ADDR_FRAME_INCR;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_client_2_burst_limit_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_2_misr_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_misr_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_bus_wr_client_2_misr_rd_word_sel;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_misr_val;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_misr_val bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_2_debug_status_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_debug_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_debug_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_2_debug_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_2_debug_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_2_DEBUG_STATUS_1;

typedef struct{
    unsigned  LAST_CONSUMED_CLIENT_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_0;

typedef struct{
    unsigned  LAST_CONSUMED_FRAME_HEADER_ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_STATUS_1;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  MODE : 1; /* 1:1 */
    unsigned  VIRTUALFRAME : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_3_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_addr_frame_header;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_addr_frame_header bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_HEADER;

typedef struct{
    unsigned  LOCAL_ID : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_frame_header_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_frame_header_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAME_HEADER_CFG;

typedef struct{
    unsigned  ADDR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_addr_image;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_addr_image bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE;

typedef struct{
    unsigned  OFFSET : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_addr_image_offset;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_addr_image_offset bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_IMAGE_OFFSET;

typedef struct{
    unsigned  WIDTH : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_buffer_width_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_buffer_width_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_WIDTH_CFG;

typedef struct{
    unsigned  HEIGHT : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_3_buffer_height_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_buffer_height_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BUFFER_HEIGHT_CFG;

typedef struct{
    unsigned  PACKER_CFG_MODE : 4; /* 3:0 */
    unsigned  PACKER_CFG_ALIGNMENT : 1; /* 4:4 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_bus_wr_client_3_packer_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_packer_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_PACKER_CFG;

typedef struct{
    unsigned  WR_STRIDE : 21; /* 20:0 */
    unsigned  UNUSED0 : 11; /* 31:21 */
} _ife_lite_ife_lite_bus_wr_client_3_wr_stride;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_wr_stride bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_WR_STRIDE;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_irq_subsample_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_irq_subsample_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_irq_subsample_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_irq_subsample_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_IRQ_SUBSAMPLE_CFG_PATTERN;

typedef struct{
    unsigned  PERIOD : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_framedrop_cfg_period;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_framedrop_cfg_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_framedrop_cfg_pattern;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_framedrop_cfg_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_FRAMEDROP_CFG_PATTERN;

typedef struct{
    unsigned  ADDR_FRAME_INCR : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_addr_frame_incr;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_addr_frame_incr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_ADDR_FRAME_INCR;

typedef struct{
    unsigned  MAX_BURST_LENGTH : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_bus_wr_client_3_burst_limit_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_burst_limit_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_BURST_LIMIT_CFG;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  SAMPLE_MODE : 2; /* 2:1 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_bus_wr_client_3_misr_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_misr_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_CFG;

typedef struct{
    unsigned  WORD_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_bus_wr_client_3_misr_rd_word_sel;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_misr_rd_word_sel bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_RD_WORD_SEL;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_misr_val;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_misr_val bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_MISR_VAL;

typedef struct{
    unsigned  STATUS_0_SEL : 8; /* 7:0 */
    unsigned  STATUS_1_SEL : 8; /* 15:8 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_bus_wr_client_3_debug_status_cfg;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_debug_status_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_CFG;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_debug_status_0;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_debug_status_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_0;

typedef struct{
    unsigned  VAL : 32; /* 31:0 */
} _ife_lite_ife_lite_bus_wr_client_3_debug_status_1;

typedef union{
    _ife_lite_ife_lite_bus_wr_client_3_debug_status_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_BUS_WR_CLIENT_3_DEBUG_STATUS_1;

typedef struct{
    unsigned  STEP : 16; /* 15:0 */
    unsigned  REV : 12; /* 27:16 */
    unsigned  GEN : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_hw_version;

typedef union{
    _ife_lite_ife_lite_csid_hw_version bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_HW_VERSION;

typedef struct{
    unsigned  CGC_MODE : 1; /* 0:0 */
    unsigned  PHY_BIST_EN : 1; /* 1:1 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_csid_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CFG0;

typedef struct{
    unsigned  GLOBAL_HALT_CMD : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_csid_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CTRL;

typedef struct{
    unsigned  IFE_CLK_DOMAIN : 1; /* 0:0 */
    unsigned  PHY_CLK_DOMAIN : 1; /* 1:1 */
    unsigned  CSID_CLK_DOMAIN : 1; /* 2:2 */
    unsigned  SW_REGS : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_csid_reset;

typedef union{
    _ife_lite_ife_lite_csid_reset bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RESET;

typedef struct{
    unsigned  RST_STROBES : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rst_strobes;

typedef union{
    _ife_lite_ife_lite_csid_rst_strobes bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RST_STROBES;

typedef struct{
    unsigned  EN : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  TEST_BUS_SEL : 24; /* 27:4 */
    unsigned  DOMAIN_SEL : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_test_bus_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_test_bus_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL;

typedef struct{
    unsigned  STATUS_VEC : 28; /* 27:0 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_csi2_rx_irq_status;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_irq_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_STATUS;

typedef struct{
    unsigned  MASK_VEC : 28; /* 27:0 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_csi2_rx_irq_mask;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_irq_mask bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_MASK;

typedef struct{
    unsigned  CLEAR_VEC : 28; /* 27:0 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_csi2_rx_irq_clear;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_irq_clear bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_CLEAR;

typedef struct{
    unsigned  SET_VEC : 28; /* 27:0 */
    unsigned  UNUSED0 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_csi2_rx_irq_set;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_irq_set bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_IRQ_SET;

typedef struct{
    unsigned  STATUS_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi0_irq_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_irq_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_STATUS;

typedef struct{
    unsigned  MASK_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi0_irq_mask;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_irq_mask bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_MASK;

typedef struct{
    unsigned  CLEAR_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi0_irq_clear;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_irq_clear bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_CLEAR;

typedef struct{
    unsigned  SET_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi0_irq_set;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_irq_set bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SET;

typedef struct{
    unsigned  STATUS_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi1_irq_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_irq_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_STATUS;

typedef struct{
    unsigned  MASK_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi1_irq_mask;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_irq_mask bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_MASK;

typedef struct{
    unsigned  CLEAR_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi1_irq_clear;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_irq_clear bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_CLEAR;

typedef struct{
    unsigned  SET_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi1_irq_set;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_irq_set bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SET;

typedef struct{
    unsigned  STATUS_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi2_irq_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_irq_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_STATUS;

typedef struct{
    unsigned  MASK_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi2_irq_mask;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_irq_mask bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_MASK;

typedef struct{
    unsigned  CLEAR_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi2_irq_clear;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_irq_clear bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_CLEAR;

typedef struct{
    unsigned  SET_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi2_irq_set;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_irq_set bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SET;

typedef struct{
    unsigned  STATUS_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi3_irq_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_irq_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_STATUS;

typedef struct{
    unsigned  MASK_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi3_irq_mask;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_irq_mask bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_MASK;

typedef struct{
    unsigned  CLEAR_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi3_irq_clear;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_irq_clear bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_CLEAR;

typedef struct{
    unsigned  SET_VEC : 15; /* 14:0 */
    unsigned  UNUSED0 : 17; /* 31:15 */
} _ife_lite_ife_lite_csid_rdi3_irq_set;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_irq_set bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SET;

typedef struct{
    unsigned  STATUS_VEC : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_top_irq_status;

typedef union{
    _ife_lite_ife_lite_csid_top_irq_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TOP_IRQ_STATUS;

typedef struct{
    unsigned  MASK_VEC : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_top_irq_mask;

typedef union{
    _ife_lite_ife_lite_csid_top_irq_mask bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TOP_IRQ_MASK;

typedef struct{
    unsigned  CLEAR_VEC : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_top_irq_clear;

typedef union{
    _ife_lite_ife_lite_csid_top_irq_clear bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TOP_IRQ_CLEAR;

typedef struct{
    unsigned  SET_VEC : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_top_irq_set;

typedef union{
    _ife_lite_ife_lite_csid_top_irq_set bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TOP_IRQ_SET;

typedef struct{
    unsigned  CLEAR : 1; /* 0:0 */
    unsigned  UNUSED0 : 3; /* 3:1 */
    unsigned  SET : 1; /* 4:4 */
    unsigned  UNUSED1 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_irq_cmd;

typedef union{
    _ife_lite_ife_lite_csid_irq_cmd bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_IRQ_CMD;

typedef struct{
    unsigned  SPARE : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_spare;

typedef union{
    _ife_lite_ife_lite_csid_spare bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_SPARE;

typedef struct{
    unsigned  NUM_ACTIVE_LANES : 2; /* 1:0 */
    unsigned  UNUSED0 : 2; /* 3:2 */
    unsigned  DL0_INPUT_SEL : 2; /* 5:4 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  DL1_INPUT_SEL : 2; /* 9:8 */
    unsigned  UNUSED2 : 2; /* 11:10 */
    unsigned  DL2_INPUT_SEL : 2; /* 13:12 */
    unsigned  UNUSED3 : 2; /* 15:14 */
    unsigned  DL3_INPUT_SEL : 2; /* 17:16 */
    unsigned  UNUSED4 : 2; /* 19:18 */
    unsigned  PHY_NUM_SEL : 2; /* 21:20 */
    unsigned  UNUSED5 : 2; /* 23:22 */
    unsigned  PHY_TYPE_SEL : 1; /* 24:24 */
    unsigned  UNUSED6 : 7; /* 31:25 */
} _ife_lite_ife_lite_csid_csi2_rx_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0;

typedef struct{
    unsigned  PACKET_ECC_CORRECTION_EN : 1; /* 0:0 */
    unsigned  DE_SCRAMBLE_EN : 1; /* 1:1 */
    unsigned  VC_MODE : 1; /* 2:2 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  COMPLETE_STREAM_EN : 1; /* 4:4 */
    unsigned  COMPLETE_STREAM_FRAME_TIMING : 1; /* 5:5 */
    unsigned  MISR_EN : 1; /* 6:6 */
    unsigned  CGC_MODE : 1; /* 7:7 */
    unsigned  UNUSED1 : 24; /* 31:8 */
} _ife_lite_ife_lite_csid_csi2_rx_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1;

typedef struct{
    unsigned  LONG_PKT_CAPTURE_EN : 1; /* 0:0 */
    unsigned  SHORT_PKT_CAPTURE_EN : 1; /* 1:1 */
    unsigned  CPHY_PKT_CAPTURE_EN : 1; /* 2:2 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  LONG_PKT_CAPTURE_VC_DT : 11; /* 14:4 */
    unsigned  SHORT_PKT_CAPTURE_VC : 5; /* 19:15 */
    unsigned  CPHY_PKT_CAPTURE_VC_DT : 11; /* 30:20 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_csi2_rx_capture_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_capture_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURE_CTRL;

typedef struct{
    unsigned  RST_STROBES : 14; /* 13:0 */
    unsigned  UNUSED0 : 18; /* 31:14 */
} _ife_lite_ife_lite_csid_csi2_rx_rst_strobes;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_rst_strobes bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_RST_STROBES;

typedef struct{
    unsigned  LANE1_SEED : 16; /* 15:0 */
    unsigned  LANE0_SEED : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_csi2_rx_de_scramble_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_de_scramble_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG0;

typedef struct{
    unsigned  LANE3_SEED : 16; /* 15:0 */
    unsigned  LANE2_SEED : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_csi2_rx_de_scramble_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_de_scramble_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_DE_SCRAMBLE_CFG1;

typedef struct{
    unsigned  WC : 16; /* 15:0 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  UNUSED0 : 5; /* 31:27 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_unmapped_long_pkt_hdr_0;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_unmapped_long_pkt_hdr_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_0;

typedef struct{
    unsigned  ECC : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_unmapped_long_pkt_hdr_1;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_unmapped_long_pkt_hdr_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_UNMAPPED_LONG_PKT_HDR_1;

typedef struct{
    unsigned  FRAME_LINE_COUNT : 16; /* 15:0 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  UNUSED0 : 5; /* 31:27 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_short_pkt_0;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_short_pkt_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_0;

typedef struct{
    unsigned  ECC : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_short_pkt_1;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_short_pkt_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_SHORT_PKT_1;

typedef struct{
    unsigned  WC : 16; /* 15:0 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  UNUSED0 : 5; /* 31:27 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_long_pkt_hdr_0;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_long_pkt_hdr_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_0;

typedef struct{
    unsigned  ECC : 6; /* 5:0 */
    unsigned  UNUSED0 : 26; /* 31:6 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_long_pkt_hdr_1;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_long_pkt_hdr_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_HDR_1;

typedef struct{
    unsigned  EXPECTED_CRC : 16; /* 15:0 */
    unsigned  CALCULATED_CRC : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_long_pkt_ftr;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_long_pkt_ftr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_LONG_PKT_FTR;

typedef struct{
    unsigned  WC : 16; /* 15:0 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  UNUSED0 : 5; /* 31:27 */
} _ife_lite_ife_lite_csid_csi2_rx_captured_cphy_pkt_hdr;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_captured_cphy_pkt_hdr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CAPTURED_CPHY_PKT_HDR;

typedef struct{
    unsigned  MISR : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_csi2_rx_lane0_misr;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_lane0_misr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE0_MISR;

typedef struct{
    unsigned  MISR : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_csi2_rx_lane1_misr;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_lane1_misr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE1_MISR;

typedef struct{
    unsigned  MISR : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_csi2_rx_lane2_misr;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_lane2_misr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE2_MISR;

typedef struct{
    unsigned  MISR : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_csi2_rx_lane3_misr;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_lane3_misr bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_LANE3_MISR;

typedef struct{
    unsigned  TOTAL_PKTS_RCVD : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_csi2_rx_total_pkts_rcvd;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_total_pkts_rcvd bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_PKTS_RCVD;

typedef struct{
    unsigned  TOTAL_RECOVERED_PKTS : 16; /* 15:0 */
    unsigned  TOTAL_UNRECOVERABLE_PKTS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_csi2_rx_stats_ecc;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_stats_ecc bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_STATS_ECC;

typedef struct{
    unsigned  TOTAL_CRC_ERRORS : 16; /* 15:0 */
    unsigned  UNUSED0 : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_csi2_rx_total_crc_errors;

typedef union{
    _ife_lite_ife_lite_csid_csi2_rx_total_crc_errors bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CSI2_RX_TOTAL_CRC_ERRORS;

typedef struct{
    unsigned  BYTE_CNTR_EN : 1; /* 0:0 */
    unsigned  FORMAT_MEASURE_EN : 1; /* 1:1 */
    unsigned  TIMESTAMP_EN : 1; /* 2:2 */
    unsigned  DROP_H_EN : 1; /* 3:3 */
    unsigned  DROP_V_EN : 1; /* 4:4 */
    unsigned  CROP_H_EN : 1; /* 5:5 */
    unsigned  CROP_V_EN : 1; /* 6:6 */
    unsigned  MISR_EN : 1; /* 7:7 */
    unsigned  CGC_MODE : 1; /* 8:8 */
    unsigned  PLAIN_ALIGNMENT : 1; /* 9:9 */
    unsigned  PLAIN_FORMAT : 2; /* 11:10 */
    unsigned  DECODE_FORMAT : 4; /* 15:12 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  DT_ID : 2; /* 28:27 */
    unsigned  EARLY_EOF_EN : 1; /* 29:29 */
    unsigned  UNUSED0 : 1; /* 30:30 */
    unsigned  EN : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_rdi0_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_CFG0;

typedef struct{
    unsigned  TIMESTAMP_STB_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_csid_rdi0_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_CFG1;

typedef struct{
    unsigned  HALT_CMD : 2; /* 1:0 */
    unsigned  HALT_MODE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_rdi0_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_CTRL;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_frame_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_frame_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi0_frame_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_frame_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_FRAME_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_irq_subsample_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_irq_subsample_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi0_irq_subsample_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_irq_subsample_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_IRQ_SUBSAMPLE_PERIOD;

typedef struct{
    unsigned  START_PIXEL : 16; /* 15:0 */
    unsigned  END_PIXEL : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_rdi0_rpp_hcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_rpp_hcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_RPP_HCROP;

typedef struct{
    unsigned  START_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  END_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi0_rpp_vcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_rpp_vcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_RPP_VCROP;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_rpp_pix_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_rpp_pix_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi0_rpp_pix_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_rpp_pix_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_RPP_PIX_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_rpp_line_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_rpp_line_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi0_rpp_line_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_rpp_line_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_RPP_LINE_DROP_PERIOD;

typedef struct{
    unsigned  CSID_CLK_RST_STB : 1; /* 0:0 */
    unsigned  IFE_CLK_RST_STB : 1; /* 1:1 */
    unsigned  MISR_RST_STB : 1; /* 2:2 */
    unsigned  FORMAT_MEASURE_RST_STB : 1; /* 3:3 */
    unsigned  TIMESTAMP_RST_STB : 1; /* 4:4 */
    unsigned  FRAMEDROP_RST_STB : 1; /* 5:5 */
    unsigned  IRQ_SUBSAMPLE_RST_STB : 1; /* 6:6 */
    unsigned  BYTE_CNTR_RST_STB : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_csid_rdi0_rst_strobes;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_rst_strobes bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_RST_STROBES;

typedef struct{
    unsigned  HALT : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_rdi0_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_STATUS;

typedef struct{
    unsigned  MISR_VAL_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_misr_val0;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_misr_val0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL0;

typedef struct{
    unsigned  MISR_VAL_63_32 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_misr_val1;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_misr_val1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL1;

typedef struct{
    unsigned  MISR_VAL_95_64 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_misr_val2;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_misr_val2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL2;

typedef struct{
    unsigned  MISR_VAL_127_96 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_misr_val3;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_misr_val3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_MISR_VAL3;

typedef struct{
    unsigned  COUNTER_ENABLES : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_csid_rdi0_format_measure_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_format_measure_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG0;

typedef struct{
    unsigned  NUM_PIX : 16; /* 15:0 */
    unsigned  NUM_LINES : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi0_format_measure_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_format_measure_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE_CFG1;

typedef struct{
    unsigned  PIX_COUNT : 16; /* 15:0 */
    unsigned  LINE_COUNT : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi0_format_measure0;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_format_measure0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE0;

typedef struct{
    unsigned  HBLANKING_MIN : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  HBLANKING_MAX : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_rdi0_format_measure1;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_format_measure1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE1;

typedef struct{
    unsigned  VBLANKING_COUNT : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi0_format_measure2;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_format_measure2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_FORMAT_MEASURE2;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_curr0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_curr0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_curr1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_curr1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_prev0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_prev0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_prev1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_prev1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_curr0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_curr0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_curr1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_curr1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_CURR1_EOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_prev0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_prev0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi0_timestamp_prev1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_timestamp_prev1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_TIMESTAMP_PREV1_EOF;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_byte_cntr_ping;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_byte_cntr_ping bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PING;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi0_byte_cntr_pong;

typedef union{
    _ife_lite_ife_lite_csid_rdi0_byte_cntr_pong bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI0_BYTE_CNTR_PONG;

typedef struct{
    unsigned  BYTE_CNTR_EN : 1; /* 0:0 */
    unsigned  FORMAT_MEASURE_EN : 1; /* 1:1 */
    unsigned  TIMESTAMP_EN : 1; /* 2:2 */
    unsigned  DROP_H_EN : 1; /* 3:3 */
    unsigned  DROP_V_EN : 1; /* 4:4 */
    unsigned  CROP_H_EN : 1; /* 5:5 */
    unsigned  CROP_V_EN : 1; /* 6:6 */
    unsigned  MISR_EN : 1; /* 7:7 */
    unsigned  CGC_MODE : 1; /* 8:8 */
    unsigned  PLAIN_ALIGNMENT : 1; /* 9:9 */
    unsigned  PLAIN_FORMAT : 2; /* 11:10 */
    unsigned  DECODE_FORMAT : 4; /* 15:12 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  DT_ID : 2; /* 28:27 */
    unsigned  EARLY_EOF_EN : 1; /* 29:29 */
    unsigned  UNUSED0 : 1; /* 30:30 */
    unsigned  EN : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_rdi1_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_CFG0;

typedef struct{
    unsigned  TIMESTAMP_STB_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_csid_rdi1_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_CFG1;

typedef struct{
    unsigned  HALT_CMD : 2; /* 1:0 */
    unsigned  HALT_MODE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_rdi1_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_CTRL;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_frame_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_frame_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi1_frame_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_frame_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_FRAME_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_irq_subsample_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_irq_subsample_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi1_irq_subsample_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_irq_subsample_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_IRQ_SUBSAMPLE_PERIOD;

typedef struct{
    unsigned  START_PIXEL : 16; /* 15:0 */
    unsigned  END_PIXEL : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_rdi1_rpp_hcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_rpp_hcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_RPP_HCROP;

typedef struct{
    unsigned  START_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  END_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi1_rpp_vcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_rpp_vcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_RPP_VCROP;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_rpp_pix_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_rpp_pix_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi1_rpp_pix_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_rpp_pix_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_RPP_PIX_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_rpp_line_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_rpp_line_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi1_rpp_line_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_rpp_line_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_RPP_LINE_DROP_PERIOD;

typedef struct{
    unsigned  CSID_CLK_RST_STB : 1; /* 0:0 */
    unsigned  IFE_CLK_RST_STB : 1; /* 1:1 */
    unsigned  MISR_RST_STB : 1; /* 2:2 */
    unsigned  FORMAT_MEASURE_RST_STB : 1; /* 3:3 */
    unsigned  TIMESTAMP_RST_STB : 1; /* 4:4 */
    unsigned  FRAMEDROP_RST_STB : 1; /* 5:5 */
    unsigned  IRQ_SUBSAMPLE_RST_STB : 1; /* 6:6 */
    unsigned  BYTE_CNTR_RST_STB : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_csid_rdi1_rst_strobes;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_rst_strobes bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_RST_STROBES;

typedef struct{
    unsigned  HALT : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_rdi1_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_STATUS;

typedef struct{
    unsigned  MISR_VAL_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_misr_val0;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_misr_val0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL0;

typedef struct{
    unsigned  MISR_VAL_63_32 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_misr_val1;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_misr_val1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL1;

typedef struct{
    unsigned  MISR_VAL_95_64 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_misr_val2;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_misr_val2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL2;

typedef struct{
    unsigned  MISR_VAL_127_96 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_misr_val3;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_misr_val3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_MISR_VAL3;

typedef struct{
    unsigned  COUNTER_ENABLES : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_csid_rdi1_format_measure_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_format_measure_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG0;

typedef struct{
    unsigned  NUM_PIX : 16; /* 15:0 */
    unsigned  NUM_LINES : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi1_format_measure_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_format_measure_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE_CFG1;

typedef struct{
    unsigned  PIX_COUNT : 16; /* 15:0 */
    unsigned  LINE_COUNT : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi1_format_measure0;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_format_measure0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE0;

typedef struct{
    unsigned  HBLANKING_MIN : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  HBLANKING_MAX : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_rdi1_format_measure1;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_format_measure1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE1;

typedef struct{
    unsigned  VBLANKING_COUNT : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi1_format_measure2;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_format_measure2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_FORMAT_MEASURE2;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_curr0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_curr0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_curr1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_curr1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_prev0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_prev0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_prev1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_prev1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_curr0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_curr0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_curr1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_curr1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_CURR1_EOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_prev0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_prev0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi1_timestamp_prev1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_timestamp_prev1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_TIMESTAMP_PREV1_EOF;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_byte_cntr_ping;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_byte_cntr_ping bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PING;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi1_byte_cntr_pong;

typedef union{
    _ife_lite_ife_lite_csid_rdi1_byte_cntr_pong bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI1_BYTE_CNTR_PONG;

typedef struct{
    unsigned  BYTE_CNTR_EN : 1; /* 0:0 */
    unsigned  FORMAT_MEASURE_EN : 1; /* 1:1 */
    unsigned  TIMESTAMP_EN : 1; /* 2:2 */
    unsigned  DROP_H_EN : 1; /* 3:3 */
    unsigned  DROP_V_EN : 1; /* 4:4 */
    unsigned  CROP_H_EN : 1; /* 5:5 */
    unsigned  CROP_V_EN : 1; /* 6:6 */
    unsigned  MISR_EN : 1; /* 7:7 */
    unsigned  CGC_MODE : 1; /* 8:8 */
    unsigned  PLAIN_ALIGNMENT : 1; /* 9:9 */
    unsigned  PLAIN_FORMAT : 2; /* 11:10 */
    unsigned  DECODE_FORMAT : 4; /* 15:12 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  DT_ID : 2; /* 28:27 */
    unsigned  EARLY_EOF_EN : 1; /* 29:29 */
    unsigned  UNUSED0 : 1; /* 30:30 */
    unsigned  EN : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_rdi2_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_CFG0;

typedef struct{
    unsigned  TIMESTAMP_STB_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_csid_rdi2_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_CFG1;

typedef struct{
    unsigned  HALT_CMD : 2; /* 1:0 */
    unsigned  HALT_MODE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_rdi2_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_CTRL;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_frame_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_frame_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi2_frame_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_frame_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_FRAME_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_irq_subsample_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_irq_subsample_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi2_irq_subsample_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_irq_subsample_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_IRQ_SUBSAMPLE_PERIOD;

typedef struct{
    unsigned  START_PIXEL : 16; /* 15:0 */
    unsigned  END_PIXEL : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_rdi2_rpp_hcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_rpp_hcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_RPP_HCROP;

typedef struct{
    unsigned  START_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  END_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi2_rpp_vcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_rpp_vcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_RPP_VCROP;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_rpp_pix_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_rpp_pix_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi2_rpp_pix_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_rpp_pix_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_RPP_PIX_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_rpp_line_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_rpp_line_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi2_rpp_line_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_rpp_line_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_RPP_LINE_DROP_PERIOD;

typedef struct{
    unsigned  COMPONENT_SWAP_EN : 1; /* 0:0 */
    unsigned  ROUNDING_MODE : 2; /* 2:1 */
    unsigned  EN : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_csid_rdi2_yuv_chroma_conversion;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_yuv_chroma_conversion bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_YUV_CHROMA_CONVERSION;

typedef struct{
    unsigned  CSID_CLK_RST_STB : 1; /* 0:0 */
    unsigned  IFE_CLK_RST_STB : 1; /* 1:1 */
    unsigned  MISR_RST_STB : 1; /* 2:2 */
    unsigned  FORMAT_MEASURE_RST_STB : 1; /* 3:3 */
    unsigned  TIMESTAMP_RST_STB : 1; /* 4:4 */
    unsigned  FRAMEDROP_RST_STB : 1; /* 5:5 */
    unsigned  IRQ_SUBSAMPLE_RST_STB : 1; /* 6:6 */
    unsigned  BYTE_CNTR_RST_STB : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_csid_rdi2_rst_strobes;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_rst_strobes bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_RST_STROBES;

typedef struct{
    unsigned  HALT : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_rdi2_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_STATUS;

typedef struct{
    unsigned  MISR_VAL_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_misr_val0;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_misr_val0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL0;

typedef struct{
    unsigned  MISR_VAL_63_32 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_misr_val1;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_misr_val1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL1;

typedef struct{
    unsigned  MISR_VAL_95_64 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_misr_val2;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_misr_val2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL2;

typedef struct{
    unsigned  MISR_VAL_127_96 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_misr_val3;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_misr_val3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_MISR_VAL3;

typedef struct{
    unsigned  COUNTER_ENABLES : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_csid_rdi2_format_measure_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_format_measure_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG0;

typedef struct{
    unsigned  NUM_PIX : 16; /* 15:0 */
    unsigned  NUM_LINES : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi2_format_measure_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_format_measure_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE_CFG1;

typedef struct{
    unsigned  PIX_COUNT : 16; /* 15:0 */
    unsigned  LINE_COUNT : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi2_format_measure0;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_format_measure0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE0;

typedef struct{
    unsigned  HBLANKING_MIN : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  HBLANKING_MAX : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_rdi2_format_measure1;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_format_measure1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE1;

typedef struct{
    unsigned  VBLANKING_COUNT : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi2_format_measure2;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_format_measure2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_FORMAT_MEASURE2;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_curr0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_curr0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_curr1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_curr1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_prev0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_prev0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_prev1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_prev1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_curr0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_curr0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_curr1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_curr1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_CURR1_EOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_prev0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_prev0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi2_timestamp_prev1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_timestamp_prev1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_TIMESTAMP_PREV1_EOF;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_byte_cntr_ping;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_byte_cntr_ping bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PING;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi2_byte_cntr_pong;

typedef union{
    _ife_lite_ife_lite_csid_rdi2_byte_cntr_pong bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI2_BYTE_CNTR_PONG;

typedef struct{
    unsigned  BYTE_CNTR_EN : 1; /* 0:0 */
    unsigned  FORMAT_MEASURE_EN : 1; /* 1:1 */
    unsigned  TIMESTAMP_EN : 1; /* 2:2 */
    unsigned  DROP_H_EN : 1; /* 3:3 */
    unsigned  DROP_V_EN : 1; /* 4:4 */
    unsigned  CROP_H_EN : 1; /* 5:5 */
    unsigned  CROP_V_EN : 1; /* 6:6 */
    unsigned  MISR_EN : 1; /* 7:7 */
    unsigned  CGC_MODE : 1; /* 8:8 */
    unsigned  PLAIN_ALIGNMENT : 1; /* 9:9 */
    unsigned  PLAIN_FORMAT : 2; /* 11:10 */
    unsigned  DECODE_FORMAT : 4; /* 15:12 */
    unsigned  DT : 6; /* 21:16 */
    unsigned  VC : 5; /* 26:22 */
    unsigned  DT_ID : 2; /* 28:27 */
    unsigned  EARLY_EOF_EN : 1; /* 29:29 */
    unsigned  UNUSED0 : 1; /* 30:30 */
    unsigned  EN : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_rdi3_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_CFG0;

typedef struct{
    unsigned  TIMESTAMP_STB_SEL : 2; /* 1:0 */
    unsigned  UNUSED0 : 30; /* 31:2 */
} _ife_lite_ife_lite_csid_rdi3_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_CFG1;

typedef struct{
    unsigned  HALT_CMD : 2; /* 1:0 */
    unsigned  HALT_MODE : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_rdi3_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_CTRL;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_frame_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_frame_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi3_frame_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_frame_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_FRAME_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_irq_subsample_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_irq_subsample_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi3_irq_subsample_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_irq_subsample_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_IRQ_SUBSAMPLE_PERIOD;

typedef struct{
    unsigned  START_PIXEL : 16; /* 15:0 */
    unsigned  END_PIXEL : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_rdi3_rpp_hcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_rpp_hcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_RPP_HCROP;

typedef struct{
    unsigned  START_LINE : 14; /* 13:0 */
    unsigned  UNUSED0 : 2; /* 15:14 */
    unsigned  END_LINE : 14; /* 29:16 */
    unsigned  UNUSED1 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi3_rpp_vcrop;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_rpp_vcrop bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_RPP_VCROP;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_rpp_pix_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_rpp_pix_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi3_rpp_pix_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_rpp_pix_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_RPP_PIX_DROP_PERIOD;

typedef struct{
    unsigned  PATTERN : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_rpp_line_drop_pattern;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_rpp_line_drop_pattern bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PATTERN;

typedef struct{
    unsigned  PERIOD : 5; /* 4:0 */
    unsigned  UNUSED0 : 27; /* 31:5 */
} _ife_lite_ife_lite_csid_rdi3_rpp_line_drop_period;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_rpp_line_drop_period bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_RPP_LINE_DROP_PERIOD;

typedef struct{
    unsigned  COMPONENT_SWAP_EN : 1; /* 0:0 */
    unsigned  ROUNDING_MODE : 2; /* 2:1 */
    unsigned  EN : 1; /* 3:3 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_csid_rdi3_yuv_chroma_conversion;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_yuv_chroma_conversion bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_YUV_CHROMA_CONVERSION;

typedef struct{
    unsigned  CSID_CLK_RST_STB : 1; /* 0:0 */
    unsigned  IFE_CLK_RST_STB : 1; /* 1:1 */
    unsigned  MISR_RST_STB : 1; /* 2:2 */
    unsigned  FORMAT_MEASURE_RST_STB : 1; /* 3:3 */
    unsigned  TIMESTAMP_RST_STB : 1; /* 4:4 */
    unsigned  FRAMEDROP_RST_STB : 1; /* 5:5 */
    unsigned  IRQ_SUBSAMPLE_RST_STB : 1; /* 6:6 */
    unsigned  BYTE_CNTR_RST_STB : 1; /* 7:7 */
    unsigned  UNUSED0 : 24; /* 31:8 */
} _ife_lite_ife_lite_csid_rdi3_rst_strobes;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_rst_strobes bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_RST_STROBES;

typedef struct{
    unsigned  HALT : 1; /* 0:0 */
    unsigned  UNUSED0 : 31; /* 31:1 */
} _ife_lite_ife_lite_csid_rdi3_status;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_status bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_STATUS;

typedef struct{
    unsigned  MISR_VAL_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_misr_val0;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_misr_val0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL0;

typedef struct{
    unsigned  MISR_VAL_63_32 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_misr_val1;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_misr_val1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL1;

typedef struct{
    unsigned  MISR_VAL_95_64 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_misr_val2;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_misr_val2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL2;

typedef struct{
    unsigned  MISR_VAL_127_96 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_misr_val3;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_misr_val3 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_MISR_VAL3;

typedef struct{
    unsigned  COUNTER_ENABLES : 4; /* 3:0 */
    unsigned  UNUSED0 : 28; /* 31:4 */
} _ife_lite_ife_lite_csid_rdi3_format_measure_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_format_measure_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG0;

typedef struct{
    unsigned  NUM_PIX : 16; /* 15:0 */
    unsigned  NUM_LINES : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi3_format_measure_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_format_measure_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE_CFG1;

typedef struct{
    unsigned  PIX_COUNT : 16; /* 15:0 */
    unsigned  LINE_COUNT : 14; /* 29:16 */
    unsigned  UNUSED0 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_rdi3_format_measure0;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_format_measure0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE0;

typedef struct{
    unsigned  HBLANKING_MIN : 12; /* 11:0 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  HBLANKING_MAX : 12; /* 27:16 */
    unsigned  UNUSED1 : 4; /* 31:28 */
} _ife_lite_ife_lite_csid_rdi3_format_measure1;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_format_measure1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE1;

typedef struct{
    unsigned  VBLANKING_COUNT : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi3_format_measure2;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_format_measure2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_FORMAT_MEASURE2;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_curr0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_curr0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_curr1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_curr1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_prev0_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_prev0_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_SOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_prev1_sof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_prev1_sof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_SOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_curr0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_curr0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_curr1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_curr1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_CURR1_EOF;

typedef struct{
    unsigned  TIMESTAMP_31_0 : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_prev0_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_prev0_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV0_EOF;

typedef struct{
    unsigned  TIMESTAMP_55_32 : 24; /* 23:0 */
    unsigned  UNUSED0 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_rdi3_timestamp_prev1_eof;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_timestamp_prev1_eof bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_TIMESTAMP_PREV1_EOF;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_byte_cntr_ping;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_byte_cntr_ping bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PING;

typedef struct{
    unsigned  BYTE_COUNT : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_rdi3_byte_cntr_pong;

typedef union{
    _ife_lite_ife_lite_csid_rdi3_byte_cntr_pong bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_RDI3_BYTE_CNTR_PONG;

typedef struct{
    unsigned  TEST_EN : 1; /* 0:0 */
    unsigned  FS_PKT_EN : 1; /* 1:1 */
    unsigned  FE_PKT_EN : 1; /* 2:2 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  NUM_ACTIVE_LANES : 2; /* 5:4 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  CYCLES_BETWEEN_PKTS : 10; /* 17:8 */
    unsigned  UNUSED2 : 2; /* 19:18 */
    unsigned  NUM_TRAIL_BYTES : 10; /* 29:20 */
    unsigned  UNUSED3 : 2; /* 31:30 */
} _ife_lite_ife_lite_csid_tpg_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_tpg_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CTRL;

typedef struct{
    unsigned  VC_NUM : 4; /* 3:0 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  NUM_ACTIVE_DTS : 2; /* 9:8 */
    unsigned  LINE_INTERLEAVING_MODE : 2; /* 11:10 */
    unsigned  UNUSED1 : 4; /* 15:12 */
    unsigned  NUM_FRAMES : 8; /* 23:16 */
    unsigned  UNUSED2 : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_tpg_vc_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_vc_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0;

typedef struct{
    unsigned  H_BLANKING_COUNT : 11; /* 10:0 */
    unsigned  UNUSED0 : 1; /* 11:11 */
    unsigned  V_BLANKING_COUNT : 10; /* 21:12 */
    unsigned  UNUSED1 : 2; /* 23:22 */
    unsigned  V_BLANK_FRAME_WIDTH_SEL : 2; /* 25:24 */
    unsigned  UNUSED2 : 6; /* 31:26 */
} _ife_lite_ife_lite_csid_tpg_vc_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_vc_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG1;

typedef struct{
    unsigned  SEED : 32; /* 31:0 */
} _ife_lite_ife_lite_csid_tpg_lfsr_seed;

typedef union{
    _ife_lite_ife_lite_csid_tpg_lfsr_seed bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_LFSR_SEED;

typedef struct{
    unsigned  FRAME_HEIGHT : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  FRAME_WIDTH : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_tpg_dt_0_cfg_0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_0_cfg_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_0;

typedef struct{
    unsigned  DATA_TYPE : 6; /* 5:0 */
    unsigned  UNUSED0 : 2; /* 7:6 */
    unsigned  ECC_XOR_MASK : 6; /* 13:8 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  CRC_XOR_MASK : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_tpg_dt_0_cfg_1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_0_cfg_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_1;

typedef struct{
    unsigned  PAYLOAD_MODE : 4; /* 3:0 */
    unsigned  USER_SPECIFIED_PAYLOAD : 8; /* 11:4 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  ENCODE_FORMAT : 4; /* 19:16 */
    unsigned  UNUSED1 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_dt_0_cfg_2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_0_cfg_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_0_CFG_2;

typedef struct{
    unsigned  FRAME_HEIGHT : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  FRAME_WIDTH : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_tpg_dt_1_cfg_0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_1_cfg_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_0;

typedef struct{
    unsigned  DATA_TYPE : 6; /* 5:0 */
    unsigned  UNUSED0 : 2; /* 7:6 */
    unsigned  ECC_XOR_MASK : 6; /* 13:8 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  CRC_XOR_MASK : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_tpg_dt_1_cfg_1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_1_cfg_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_1;

typedef struct{
    unsigned  PAYLOAD_MODE : 4; /* 3:0 */
    unsigned  USER_SPECIFIED_PAYLOAD : 8; /* 11:4 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  ENCODE_FORMAT : 4; /* 19:16 */
    unsigned  UNUSED1 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_dt_1_cfg_2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_1_cfg_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_1_CFG_2;

typedef struct{
    unsigned  FRAME_HEIGHT : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  FRAME_WIDTH : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_tpg_dt_2_cfg_0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_2_cfg_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_0;

typedef struct{
    unsigned  DATA_TYPE : 6; /* 5:0 */
    unsigned  UNUSED0 : 2; /* 7:6 */
    unsigned  ECC_XOR_MASK : 6; /* 13:8 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  CRC_XOR_MASK : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_tpg_dt_2_cfg_1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_2_cfg_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_1;

typedef struct{
    unsigned  PAYLOAD_MODE : 4; /* 3:0 */
    unsigned  USER_SPECIFIED_PAYLOAD : 8; /* 11:4 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  ENCODE_FORMAT : 4; /* 19:16 */
    unsigned  UNUSED1 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_dt_2_cfg_2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_2_cfg_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_2_CFG_2;

typedef struct{
    unsigned  FRAME_HEIGHT : 15; /* 14:0 */
    unsigned  UNUSED0 : 1; /* 15:15 */
    unsigned  FRAME_WIDTH : 15; /* 30:16 */
    unsigned  UNUSED1 : 1; /* 31:31 */
} _ife_lite_ife_lite_csid_tpg_dt_3_cfg_0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_3_cfg_0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_0;

typedef struct{
    unsigned  DATA_TYPE : 6; /* 5:0 */
    unsigned  UNUSED0 : 2; /* 7:6 */
    unsigned  ECC_XOR_MASK : 6; /* 13:8 */
    unsigned  UNUSED1 : 2; /* 15:14 */
    unsigned  CRC_XOR_MASK : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_tpg_dt_3_cfg_1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_3_cfg_1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_1;

typedef struct{
    unsigned  PAYLOAD_MODE : 4; /* 3:0 */
    unsigned  USER_SPECIFIED_PAYLOAD : 8; /* 11:4 */
    unsigned  UNUSED0 : 4; /* 15:12 */
    unsigned  ENCODE_FORMAT : 4; /* 19:16 */
    unsigned  UNUSED1 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_dt_3_cfg_2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_dt_3_cfg_2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_DT_3_CFG_2;

typedef struct{
    unsigned  UNICOLOR_BAR_SEL : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  UNICOLOR_BAR_EN : 1; /* 4:4 */
    unsigned  SPLIT_EN : 1; /* 5:5 */
    unsigned  UNUSED1 : 2; /* 7:6 */
    unsigned  ROTATE_PERIOD : 6; /* 13:8 */
    unsigned  UNUSED2 : 18; /* 31:14 */
} _ife_lite_ife_lite_csid_tpg_color_bars_cfg;

typedef union{
    _ife_lite_ife_lite_csid_tpg_color_bars_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BARS_CFG;

typedef struct{
    unsigned  MODE : 2; /* 1:0 */
    unsigned  PATTERN_SEL : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_tpg_color_box_cfg;

typedef union{
    _ife_lite_ife_lite_csid_tpg_color_box_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_COLOR_BOX_CFG;

typedef struct{
    unsigned  PIX_PATTERN : 3; /* 2:0 */
    unsigned  UNUSED0 : 1; /* 3:3 */
    unsigned  GAIN : 4; /* 7:4 */
    unsigned  NUM_NOISE_BITS : 4; /* 11:8 */
    unsigned  NOISE_EN : 1; /* 12:12 */
    unsigned  UNUSED1 : 19; /* 31:13 */
} _ife_lite_ife_lite_csid_tpg_common_gen_cfg;

typedef union{
    _ife_lite_ife_lite_csid_tpg_common_gen_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_COMMON_GEN_CFG;

typedef struct{
    unsigned  MODE : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_tpg_cgen0_cfg;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen0_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_CFG;

typedef struct{
    unsigned  X0 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen0_x0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen0_x0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X0;

typedef struct{
    unsigned  X1 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen0_x1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen0_x1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X1;

typedef struct{
    unsigned  X2 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen0_x2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen0_x2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_X2;

typedef struct{
    unsigned  XY : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen0_xy;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen0_xy bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_XY;

typedef struct{
    unsigned  Y1 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen0_y1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen0_y1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y1;

typedef struct{
    unsigned  Y2 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen0_y2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen0_y2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN0_Y2;

typedef struct{
    unsigned  MODE : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_tpg_cgen1_cfg;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen1_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_CFG;

typedef struct{
    unsigned  X0 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen1_x0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen1_x0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X0;

typedef struct{
    unsigned  X1 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen1_x1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen1_x1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X1;

typedef struct{
    unsigned  X2 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen1_x2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen1_x2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_X2;

typedef struct{
    unsigned  XY : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen1_xy;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen1_xy bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_XY;

typedef struct{
    unsigned  Y1 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen1_y1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen1_y1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y1;

typedef struct{
    unsigned  Y2 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen1_y2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen1_y2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN1_Y2;

typedef struct{
    unsigned  MODE : 3; /* 2:0 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_tpg_cgen2_cfg;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen2_cfg bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_CFG;

typedef struct{
    unsigned  X0 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen2_x0;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen2_x0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X0;

typedef struct{
    unsigned  X1 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen2_x1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen2_x1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X1;

typedef struct{
    unsigned  X2 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen2_x2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen2_x2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_X2;

typedef struct{
    unsigned  XY : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen2_xy;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen2_xy bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_XY;

typedef struct{
    unsigned  Y1 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen2_y1;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen2_y1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y1;

typedef struct{
    unsigned  Y2 : 20; /* 19:0 */
    unsigned  UNUSED0 : 12; /* 31:20 */
} _ife_lite_ife_lite_csid_tpg_cgen2_y2;

typedef union{
    _ife_lite_ife_lite_csid_tpg_cgen2_y2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_TPG_CGEN2_Y2;

typedef struct{
    unsigned  SEED_DATA : 16; /* 15:0 */
    unsigned  UNUSED0 : 8; /* 23:16 */
    unsigned  POLY_SEL : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_dphy_bist_l0_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l0_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG0;

typedef struct{
    unsigned  WORD_COUNT_INIT : 16; /* 15:0 */
    unsigned  PATTERN_HEADER : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l0_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l0_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG1;

typedef struct{
    unsigned  CHECKER_CROSS8 : 1; /* 0:0 */
    unsigned  CHECKER_MODE : 1; /* 1:1 */
    unsigned  CHECKER_INVERT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l0_cfg2;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l0_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CFG2;

typedef struct{
    unsigned  CHECKER_ENABLE : 1; /* 0:0 */
    unsigned  CHECKER_CAPTURE : 1; /* 1:1 */
    unsigned  CLR_ERROR_COUNT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l0_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l0_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_CTRL;

typedef struct{
    unsigned  ERROR_COUNT : 16; /* 15:0 */
    unsigned  WORD_COUNT_STATUS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l0_status0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l0_status0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS0;

typedef struct{
    unsigned  ERROR_FLAG : 1; /* 0:0 */
    unsigned  SEED_ERROR : 1; /* 1:1 */
    unsigned  ZERO_LFSR_FLAG : 1; /* 2:2 */
    unsigned  CHECKER_DONE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  CHECKER_STATUS : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _ife_lite_ife_lite_csid_dphy_bist_l0_status1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l0_status1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L0_STATUS1;

typedef struct{
    unsigned  SEED_DATA : 16; /* 15:0 */
    unsigned  UNUSED0 : 8; /* 23:16 */
    unsigned  POLY_SEL : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_dphy_bist_l1_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l1_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG0;

typedef struct{
    unsigned  WORD_COUNT_INIT : 16; /* 15:0 */
    unsigned  PATTERN_HEADER : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l1_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l1_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG1;

typedef struct{
    unsigned  CHECKER_CROSS8 : 1; /* 0:0 */
    unsigned  CHECKER_MODE : 1; /* 1:1 */
    unsigned  CHECKER_INVERT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l1_cfg2;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l1_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CFG2;

typedef struct{
    unsigned  CHECKER_ENABLE : 1; /* 0:0 */
    unsigned  CHECKER_CAPTURE : 1; /* 1:1 */
    unsigned  CLR_ERROR_COUNT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l1_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l1_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_CTRL;

typedef struct{
    unsigned  ERROR_COUNT : 16; /* 15:0 */
    unsigned  WORD_COUNT_STATUS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l1_status0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l1_status0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS0;

typedef struct{
    unsigned  ERROR_FLAG : 1; /* 0:0 */
    unsigned  SEED_ERROR : 1; /* 1:1 */
    unsigned  ZERO_LFSR_FLAG : 1; /* 2:2 */
    unsigned  CHECKER_DONE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  CHECKER_STATUS : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _ife_lite_ife_lite_csid_dphy_bist_l1_status1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l1_status1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L1_STATUS1;

typedef struct{
    unsigned  SEED_DATA : 16; /* 15:0 */
    unsigned  UNUSED0 : 8; /* 23:16 */
    unsigned  POLY_SEL : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_dphy_bist_l2_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l2_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG0;

typedef struct{
    unsigned  WORD_COUNT_INIT : 16; /* 15:0 */
    unsigned  PATTERN_HEADER : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l2_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l2_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG1;

typedef struct{
    unsigned  CHECKER_CROSS8 : 1; /* 0:0 */
    unsigned  CHECKER_MODE : 1; /* 1:1 */
    unsigned  CHECKER_INVERT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l2_cfg2;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l2_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CFG2;

typedef struct{
    unsigned  CHECKER_ENABLE : 1; /* 0:0 */
    unsigned  CHECKER_CAPTURE : 1; /* 1:1 */
    unsigned  CLR_ERROR_COUNT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l2_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l2_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_CTRL;

typedef struct{
    unsigned  ERROR_COUNT : 16; /* 15:0 */
    unsigned  WORD_COUNT_STATUS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l2_status0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l2_status0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS0;

typedef struct{
    unsigned  ERROR_FLAG : 1; /* 0:0 */
    unsigned  SEED_ERROR : 1; /* 1:1 */
    unsigned  ZERO_LFSR_FLAG : 1; /* 2:2 */
    unsigned  CHECKER_DONE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  CHECKER_STATUS : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _ife_lite_ife_lite_csid_dphy_bist_l2_status1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l2_status1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L2_STATUS1;

typedef struct{
    unsigned  SEED_DATA : 16; /* 15:0 */
    unsigned  UNUSED0 : 8; /* 23:16 */
    unsigned  POLY_SEL : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_dphy_bist_l3_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l3_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG0;

typedef struct{
    unsigned  WORD_COUNT_INIT : 16; /* 15:0 */
    unsigned  PATTERN_HEADER : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l3_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l3_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG1;

typedef struct{
    unsigned  CHECKER_CROSS8 : 1; /* 0:0 */
    unsigned  CHECKER_MODE : 1; /* 1:1 */
    unsigned  CHECKER_INVERT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l3_cfg2;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l3_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CFG2;

typedef struct{
    unsigned  CHECKER_ENABLE : 1; /* 0:0 */
    unsigned  CHECKER_CAPTURE : 1; /* 1:1 */
    unsigned  CLR_ERROR_COUNT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_dphy_bist_l3_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l3_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_CTRL;

typedef struct{
    unsigned  ERROR_COUNT : 16; /* 15:0 */
    unsigned  WORD_COUNT_STATUS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_dphy_bist_l3_status0;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l3_status0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS0;

typedef struct{
    unsigned  ERROR_FLAG : 1; /* 0:0 */
    unsigned  SEED_ERROR : 1; /* 1:1 */
    unsigned  ZERO_LFSR_FLAG : 1; /* 2:2 */
    unsigned  CHECKER_DONE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  CHECKER_STATUS : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _ife_lite_ife_lite_csid_dphy_bist_l3_status1;

typedef union{
    _ife_lite_ife_lite_csid_dphy_bist_l3_status1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_DPHY_BIST_L3_STATUS1;

typedef struct{
    unsigned  SEED_DATA : 24; /* 23:0 */
    unsigned  POLY_SEL : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_cphy_bist_l0_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l0_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG0;

typedef struct{
    unsigned  WORD_COUNT_INIT : 16; /* 15:0 */
    unsigned  PATTERN_HEADER2 : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_cphy_bist_l0_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l0_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG1;

typedef struct{
    unsigned  HEADER_MODE : 1; /* 0:0 */
    unsigned  DOUBLE_SYNC_MODE : 1; /* 1:1 */
    unsigned  SYNC_DETECTED : 1; /* 2:2 */
    unsigned  SECOND_SYNC_FLAG : 1; /* 3:3 */
    unsigned  POST_DETECTED : 1; /* 4:4 */
    unsigned  CHECKER_CROSS16 : 1; /* 5:5 */
    unsigned  CHECKER_MODE : 1; /* 6:6 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _ife_lite_ife_lite_csid_cphy_bist_l0_cfg2;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l0_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CFG2;

typedef struct{
    unsigned  CHECKER_ENABLE : 1; /* 0:0 */
    unsigned  CHECKER_CAPTURE : 1; /* 1:1 */
    unsigned  CLR_ERROR_COUNT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_cphy_bist_l0_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l0_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_CTRL;

typedef struct{
    unsigned  ERROR_COUNT : 16; /* 15:0 */
    unsigned  WORD_COUNT_STATUS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_cphy_bist_l0_status0;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l0_status0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS0;

typedef struct{
    unsigned  ERROR_FLAG : 1; /* 0:0 */
    unsigned  SEED_ERROR : 1; /* 1:1 */
    unsigned  ZERO_LFSR_FLAG : 1; /* 2:2 */
    unsigned  CHECKER_DONE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  CHECKER_STATUS : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _ife_lite_ife_lite_csid_cphy_bist_l0_status1;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l0_status1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L0_STATUS1;

typedef struct{
    unsigned  SEED_DATA : 24; /* 23:0 */
    unsigned  POLY_SEL : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_cphy_bist_l1_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l1_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG0;

typedef struct{
    unsigned  WORD_COUNT_INIT : 16; /* 15:0 */
    unsigned  PATTERN_HEADER2 : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_cphy_bist_l1_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l1_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG1;

typedef struct{
    unsigned  HEADER_MODE : 1; /* 0:0 */
    unsigned  DOUBLE_SYNC_MODE : 1; /* 1:1 */
    unsigned  SYNC_DETECTED : 1; /* 2:2 */
    unsigned  SECOND_SYNC_FLAG : 1; /* 3:3 */
    unsigned  POST_DETECTED : 1; /* 4:4 */
    unsigned  CHECKER_CROSS16 : 1; /* 5:5 */
    unsigned  CHECKER_MODE : 1; /* 6:6 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _ife_lite_ife_lite_csid_cphy_bist_l1_cfg2;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l1_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CFG2;

typedef struct{
    unsigned  CHECKER_ENABLE : 1; /* 0:0 */
    unsigned  CHECKER_CAPTURE : 1; /* 1:1 */
    unsigned  CLR_ERROR_COUNT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_cphy_bist_l1_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l1_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_CTRL;

typedef struct{
    unsigned  ERROR_COUNT : 16; /* 15:0 */
    unsigned  WORD_COUNT_STATUS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_cphy_bist_l1_status0;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l1_status0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS0;

typedef struct{
    unsigned  ERROR_FLAG : 1; /* 0:0 */
    unsigned  SEED_ERROR : 1; /* 1:1 */
    unsigned  ZERO_LFSR_FLAG : 1; /* 2:2 */
    unsigned  CHECKER_DONE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  CHECKER_STATUS : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _ife_lite_ife_lite_csid_cphy_bist_l1_status1;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l1_status1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L1_STATUS1;

typedef struct{
    unsigned  SEED_DATA : 24; /* 23:0 */
    unsigned  POLY_SEL : 8; /* 31:24 */
} _ife_lite_ife_lite_csid_cphy_bist_l2_cfg0;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l2_cfg0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG0;

typedef struct{
    unsigned  WORD_COUNT_INIT : 16; /* 15:0 */
    unsigned  PATTERN_HEADER2 : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_cphy_bist_l2_cfg1;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l2_cfg1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG1;

typedef struct{
    unsigned  HEADER_MODE : 1; /* 0:0 */
    unsigned  DOUBLE_SYNC_MODE : 1; /* 1:1 */
    unsigned  SYNC_DETECTED : 1; /* 2:2 */
    unsigned  SECOND_SYNC_FLAG : 1; /* 3:3 */
    unsigned  POST_DETECTED : 1; /* 4:4 */
    unsigned  CHECKER_CROSS16 : 1; /* 5:5 */
    unsigned  CHECKER_MODE : 1; /* 6:6 */
    unsigned  UNUSED0 : 25; /* 31:7 */
} _ife_lite_ife_lite_csid_cphy_bist_l2_cfg2;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l2_cfg2 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CFG2;

typedef struct{
    unsigned  CHECKER_ENABLE : 1; /* 0:0 */
    unsigned  CHECKER_CAPTURE : 1; /* 1:1 */
    unsigned  CLR_ERROR_COUNT : 1; /* 2:2 */
    unsigned  UNUSED0 : 29; /* 31:3 */
} _ife_lite_ife_lite_csid_cphy_bist_l2_ctrl;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l2_ctrl bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_CTRL;

typedef struct{
    unsigned  ERROR_COUNT : 16; /* 15:0 */
    unsigned  WORD_COUNT_STATUS : 16; /* 31:16 */
} _ife_lite_ife_lite_csid_cphy_bist_l2_status0;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l2_status0 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS0;

typedef struct{
    unsigned  ERROR_FLAG : 1; /* 0:0 */
    unsigned  SEED_ERROR : 1; /* 1:1 */
    unsigned  ZERO_LFSR_FLAG : 1; /* 2:2 */
    unsigned  CHECKER_DONE : 1; /* 3:3 */
    unsigned  UNUSED0 : 4; /* 7:4 */
    unsigned  CHECKER_STATUS : 3; /* 10:8 */
    unsigned  UNUSED1 : 21; /* 31:11 */
} _ife_lite_ife_lite_csid_cphy_bist_l2_status1;

typedef union{
    _ife_lite_ife_lite_csid_cphy_bist_l2_status1 bitfields,bits;
    unsigned int u32All;

} IFE_LITE_IFE_LITE_CSID_CPHY_BIST_L2_STATUS1;

/*----------------------------------------------------------------------
        ENUM Data Structures
----------------------------------------------------------------------*/

typedef enum{
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_SENSOR_SEL_RDI_3  = 0x0,
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_SENSOR_SEL_RDI_0  = 0x1,
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_SENSOR_SEL_RDI_1  = 0x2,
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_SENSOR_SEL_RDI_2  = 0x3
} IFE_LITE_IFE_LITE_VFE_DIAG_CFG_SENSOR_SEL_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI3_FRM_CNT_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI3_FRM_CNT_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI3_FRM_CNT_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI0_FRM_CNT_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI0_FRM_CNT_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI0_FRM_CNT_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI1_FRM_CNT_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI1_FRM_CNT_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI1_FRM_CNT_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI2_FRM_CNT_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI2_FRM_CNT_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_VFE_DIAG_CFG_RDI2_FRM_CNT_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_ALL_ZEROS  = 0x0,
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_SENSOR_TEST_BUS  = 0x1,
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_MODULE_TEST_BUS  = 0x2,
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_BUS_IF_TEST_BUS  = 0x3,
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_RESERVED  = 0x4,
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_IRQ_TEST_BUS  = 0x5,
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_DEAD_BEEF  = 0x6,
    IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_ALL_ONES  = 0x7
} IFE_LITE_IFE_LITE_VFE_TESTBUS_SEL_DOMAIN_SEL_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_CFG0_CGC_MODE_DYNAMIC_GATING  = 0x0,
    IFE_LITE_IFE_LITE_CSID_CFG0_CGC_MODE_ALWAYS_ON  = 0x1
} IFE_LITE_IFE_LITE_CSID_CFG0_CGC_MODE_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_CSID_TEST_BUS_CTRL_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_PHY_TYPE_SEL_DPHY  = 0x0,
    IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_PHY_TYPE_SEL_CPHY  = 0x1
} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG0_PHY_TYPE_SEL_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_CGC_MODE_DYNAMIC_GATING  = 0x0,
    IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_CGC_MODE_ALWAYS_ON  = 0x1
} IFE_LITE_IFE_LITE_CSID_CSI2_RX_CFG1_CGC_MODE_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CGC_MODE_DYNAMIC_GATING  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CGC_MODE_ALWAYS_ON  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_CGC_MODE_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_PLAIN_ALIGNMENT_LSB_ALIGNED  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_PLAIN_ALIGNMENT_MSB_ALIGNED  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_PLAIN_ALIGNMENT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_UNCOMPRESSED_6_BIT  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_UNCOMPRESSED_8_BIT  = 0x1,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_UNCOMPRESSED_10_BIT  = 0x2,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_UNCOMPRESSED_12_BIT  = 0x3,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_UNCOMPRESSED_14_BIT  = 0x4,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_UNCOMPRESSED_16_BIT  = 0x5,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_UNCOMPRESSED_20_BIT  = 0x6,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_DPCM_10_6_10  = 0x7,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_DPCM_10_8_10  = 0x8,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_DPCM_12_6_12  = 0x9,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_DPCM_12_8_12  = 0xa,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_DPCM_14_8_14  = 0xb,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_DPCM_14_10_14  = 0xc,
    IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_PAYLOAD_ONLY  = 0xf
} IFE_LITE_IFE_LITE_CSID_RDI0_CFG0_DECODE_FORMAT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CGC_MODE_DYNAMIC_GATING  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CGC_MODE_ALWAYS_ON  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_CGC_MODE_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_PLAIN_ALIGNMENT_LSB_ALIGNED  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_PLAIN_ALIGNMENT_MSB_ALIGNED  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_PLAIN_ALIGNMENT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_UNCOMPRESSED_6_BIT  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_UNCOMPRESSED_8_BIT  = 0x1,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_UNCOMPRESSED_10_BIT  = 0x2,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_UNCOMPRESSED_12_BIT  = 0x3,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_UNCOMPRESSED_14_BIT  = 0x4,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_UNCOMPRESSED_16_BIT  = 0x5,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_UNCOMPRESSED_20_BIT  = 0x6,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_DPCM_10_6_10  = 0x7,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_DPCM_10_8_10  = 0x8,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_DPCM_12_6_12  = 0x9,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_DPCM_12_8_12  = 0xa,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_DPCM_14_8_14  = 0xb,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_DPCM_14_10_14  = 0xc,
    IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_PAYLOAD_ONLY  = 0xf
} IFE_LITE_IFE_LITE_CSID_RDI1_CFG0_DECODE_FORMAT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CGC_MODE_DYNAMIC_GATING  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CGC_MODE_ALWAYS_ON  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_CGC_MODE_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_PLAIN_ALIGNMENT_LSB_ALIGNED  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_PLAIN_ALIGNMENT_MSB_ALIGNED  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_PLAIN_ALIGNMENT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_UNCOMPRESSED_6_BIT  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_UNCOMPRESSED_8_BIT  = 0x1,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_UNCOMPRESSED_10_BIT  = 0x2,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_UNCOMPRESSED_12_BIT  = 0x3,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_UNCOMPRESSED_14_BIT  = 0x4,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_UNCOMPRESSED_16_BIT  = 0x5,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_UNCOMPRESSED_20_BIT  = 0x6,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_DPCM_10_6_10  = 0x7,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_DPCM_10_8_10  = 0x8,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_DPCM_12_6_12  = 0x9,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_DPCM_12_8_12  = 0xa,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_DPCM_14_8_14  = 0xb,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_DPCM_14_10_14  = 0xc,
    IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_PAYLOAD_ONLY  = 0xf
} IFE_LITE_IFE_LITE_CSID_RDI2_CFG0_DECODE_FORMAT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CGC_MODE_DYNAMIC_GATING  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CGC_MODE_ALWAYS_ON  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_CGC_MODE_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_PLAIN_ALIGNMENT_LSB_ALIGNED  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_PLAIN_ALIGNMENT_MSB_ALIGNED  = 0x1
} IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_PLAIN_ALIGNMENT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_UNCOMPRESSED_6_BIT  = 0x0,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_UNCOMPRESSED_8_BIT  = 0x1,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_UNCOMPRESSED_10_BIT  = 0x2,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_UNCOMPRESSED_12_BIT  = 0x3,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_UNCOMPRESSED_14_BIT  = 0x4,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_UNCOMPRESSED_16_BIT  = 0x5,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_UNCOMPRESSED_20_BIT  = 0x6,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_DPCM_10_6_10  = 0x7,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_DPCM_10_8_10  = 0x8,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_DPCM_12_6_12  = 0x9,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_DPCM_12_8_12  = 0xa,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_DPCM_14_8_14  = 0xb,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_DPCM_14_10_14  = 0xc,
    IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_PAYLOAD_ONLY  = 0xf
} IFE_LITE_IFE_LITE_CSID_RDI3_CFG0_DECODE_FORMAT_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_TPG_CTRL_TEST_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_CSID_TPG_CTRL_TEST_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_CSID_TPG_CTRL_TEST_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FS_PKT_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FS_PKT_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FS_PKT_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FE_PKT_EN_DISABLE  = 0x0,
    IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FE_PKT_EN_ENABLE  = 0x1
} IFE_LITE_IFE_LITE_CSID_TPG_CTRL_FE_PKT_EN_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_ACTIVE_DTS_DT_0_ENABLED  = 0x0,
    IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_ACTIVE_DTS_DT_0_1_ENABLED  = 0x1,
    IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_ACTIVE_DTS_DT_0_1_2_ENABLED  = 0x2,
    IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_ACTIVE_DTS_DT_0_1_2_3_ENABLED  = 0x3
} IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_NUM_ACTIVE_DTS_ENUM;


typedef enum{
    IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_LINE_INTERLEAVING_MODE_INTERLEAVED  = 0x0,
    IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_LINE_INTERLEAVING_MODE_ONE_SHOT  = 0x1
} IFE_LITE_IFE_LITE_CSID_TPG_VC_CFG0_LINE_INTERLEAVING_MODE_ENUM;

#endif // TITAN170_IFE_LITE_H
